Get email delivery of the Cadence blog featured here
The following post is an excerpt of “Methodology for Analyzing and Quantifying Design Style Changes and Complexity using Topological Patterns” that Jason Cain, Principal Member of the Technical Staff with AMD gave earlier at the SPIE conference. I felt it was worthwhile to post this summary for all because it covers an important challenge that customers are facing.
At AMD and other fabless design companies, a lot of effort is spent to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth) because the impact on yield and performance is tremendous.
One important goal is to reduce the types and complexity of design patterns in use, while establishing and understanding what sets of patterns are necessary for designers. Further, over time design styles can and do change and therefore it also important to be able to identify when new patterns have been introduced and what they are.
In addition, early in the design cycle, the design of high yielding standard cells is critical for design companies. This is often done before the process and related litho models and rules have fully matured.
Cadence Diffing aNd Analytics flow (DNA) based on Cadence Pattern Analysis introduces a novel methodology for full chip high performance topological pattern analysis that can be used to analyze design styles in order to quantify and measure design changes and the degree of layout regularization. This new design for manufacturing approach understands what patterns are common and which patterns are unique helps provide process-agnostic guidance to designers looking for ways to improve their design robustness. This pattern analysis methodology can be applied to the process of correlating pattern usage and cell usage to help designers understand what patterns are important and to suggest where and how patterns can be improved to increase layout regularization.
For more information, you can check the full paper: Pattern-Based Analytics to Estimate and Track Yield Risk of Designs Down to 7nm.
If you would like to discuss this topic feel free to send a message at firstname.lastname@example.org or please visit us at SPIE 2018 in San Jose, Ca in March.