Silicon Signoff Blogs

Is there anything called pindrop silence? Oh yes, I experienced the sound of silence when I visited an acoustic anechoic chamber. I could hear my own heartbeat, vibration of my cells, and the fluids running through my veins. The absence of sound was deafening, it was a unique sensory experience. That’s when I realized the degree of the sound level around us in this real world.

Just like noise triggers a stress response in certain parts of our brainstem impacting our health, noise has a huge impact on electronic circuitry as well, especially for analog and RF circuits. With 5G, comes the next generation of mobile phones, and more than 100X connected devices per unit area operating at very high frequencies. With the increase in number of devices you carry around and devices connected through internet of things (IoT), an ever-evolving technology, the conventional methods to prevent RF interferences are put to test.

RF spurs are difficult to predict and are very often observed during final silicon testing, causing IC re-spins, delaying time to market, and increasing cost to market. In wireless RF transceivers, the high purity of the local oscillator is very critical. RF designers often design on-chip LO synthesizers considering the cost and size factor. When a sensitive RF synthesizer shares the die with digital circuitry, LO purity gets affected due to the disturbances, which in turn results in generating spurious frequencies. Spurious frequencies can result in creating an error in receiver data, degrading reception BER, and in a transceiver, an unwanted signal can appear above a strict interference limit, causing a compliance mask violation.

Spurs are usually corrected by placing extra components on PCB to overcome interference limit on performance, for example, discrete/SAW RF filters. These filters are relatively expensive. If the spur is too problematic, it may need an IC re-spin, which is costly for NRE and impacts time to market as well. Frequency planning is another option, but an additional clock source (xtal) may be needed to avoid spur 

affecting performance. All these have an impact on cost and time. As many of the design engineers have already experienced, practically, it is very difficult to accurately model effects. So, what’s the solution?

Prediction of RF Spurs Using Substrate Noise Analysis

The Cadence Quantus Extraction Solution is the only solution available today to model substrate noise accurately in a tightly integrated Virtuoso® Flow. As discussed in the above paragraph, the convergence of analog and digital circuits on the same chip in conjunction with the lower process geometries is compounding the noise crisis. This not only generates spikes but noise sensitivity as well.

Quantus Extraction has the substrate extraction capability to provide analysis capabilities to RF designers.

Quantus Substrate Noise Distribution (SND) provides visualization of the irregularities or unwanted frequency distribution in substrate in the form of a 2D color map or a 1D distribution graph format.

Quantus Substrate Noise Analysis (SNA) can be used to verify observed spike noise in the silent ground of victim analog block.

In order to predict the spurs, RF designers need an evaluation method to identify the impact of the spur on their design. Quantus SNA provides RF designers with the ability to analyze the qualitative effects of noise propagation.

The above diagram gives a view of how to minimize the impact of substrate parasitic on the designs by using various mitigation strategies. This methodology helps RF designers to simplify the assumptions and to roughly predict the problematic area or component that helps them to come up with a suitable mitigation strategy. With the Quantus Extraction + substrate option, RF designers can determine what the attenuation profiles are. This allows for an approximate understanding of critical spacing and placement of guard rings.

A Real Customer Success Story

Let’s look at the results obtained using Quantus Extraction by one of our customers who is using this functionality in production, Adesto Technologies (Noel O’Riordan and Eric Downey)

In the test cases, they considered two scenarios: The first design, without SNA simulation, showed borderline spur due to substrate disturbance from digital clock.
The second design, with a change based on SNA simulation, showed reduced spur at an admissible level.     The same results as indicated by Quantus SNA simulation were obtained when the lab measurements were taken for both the silicon.

If you are interested to know more about the 5G functionality of Quantus Extraction, contact your Cadence representative.