Silicon Signoff Blogs

At the upcoming SPIE Advanced Lithography conference (Feb. 25 – March 1, San Jose, CA) you can hear from experts in the field on how these challenges are being addressed. 

On Feb. 28 you can hear from AMD and Cadence on “Applying machine learning to pattern analysis for automated in-design layout optimization”.  This presentation is a continuation of last years’ presentation and the focus of my last two blogs about pattern analysis and design profiling.  This year, we focused our work on optimization. We explore adapting the concept of entropy to measure the pattern diversity of a design, applying machine learning to identify the best candidates for pattern replacement, and developing a flow to optimize designs to make them more manufacturable.

Additionally, several other papers will focus on DPTCO and outline how Cadence high-performance and high-capacity pattern analysis technology can be leveraged to:

• Simplify and accelerate OPC tuning, monitoring, and optimization with NXP
• Shorten IP block detection, verification, and variability analysis with Silterra
• Reduce Optical Proximity Correction Run-Time with Winbond

Results from work done with place and route for 7nm and 5nm processes will also be presented in joint papers with GLOBALFOUNDRIES and IMEC respectively. 

Another presentation will review Cadence technology that assists with Layout Optimization such as the presentation jointly given with SMIC on pin routability and pin access analysis on standard cells.

All in all, a lot of work has been done to address the yield and manufacturing challenges that moving to advanced nodes may pose.  Come visit us at booth #106 or, if you want to discuss any of our results in more detail, schedule an onsite private meeting by emailing spie@cadence.com.  Hope to see you there!