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It takes the proverbial village to build complex chips and systems these days. Imagination and Cadence are critical parts of the ecosystem that build many of the technologies that make our life as consumers more productive, comfortable, and safe.
In my career, I had run into Colin McKellar when we were both focused more on hardware-assisted verification. We recently repeated our fireside chat from seven years ago, with a broader set of topics. Under Colin's leadership, Imagination's application of EDA offerings had always been quite advanced, as evidenced in the combined usage of emulation and prototyping, which, of course, has become pretty much mainstream.
Both Imagination and Cadence look at the world through industry verticals and technology horizontals. My team and I deal with solutions for verticals: Consumer, hyperscale, mobile, networking, automotive, aerospace/defense, industrial, and health, as well as technology horizontals like AI/ML, digital twins, safety, 3D-IC, and low-power. We align well with Imagination in the automotive, mobile/consumer, and computing for data centers and desktops. Imagination horizontals are AI/ML, CPU, and graphics offerings across verticals. And of course, as an IP provider, issues like mainstream versus premium performance matter considerably in markets like mobile and consumer. I recently attended the embedded world 2022 conference in Nuernberg, at which both Imagination and Cadence were exhibitors, and the Imagination booth clearly showed the three key themes of automotive, graphics, and AI - see above.
Data Centers, Hyperscale Computing, and Hyperconnectivity
As described in previous blogs, the era of hyperscale computing is so fascinating for EDA and IP because of the diversity of computing requirements—graphics, acceleration, and specialized AI/ML augment "classic" computing. And connectivity is critical, given that the data movement within the data center and to and from the compute areas is majorly impacted. While Cadence enables these amazingly complex chips with tools for high capacity implementation and verification, Imagination addresses this area from the three angles of graphics, connectivity, and optimized processors for AI/ML computing. Requirements to be met on the graphics side include aspects of virtualization, security, and solid APIs for cloud-based gaming. Of course, low-power consumption is critical, and Imagination has been traditionally strong here. Ethernet is the trusted protocol of choice for connectivity, and Imagination has a strong portfolio of packet processors here. Imagination addresses AI/ML and general computing with specific GPUs and RISC V, and one can imagine a strong position here, especially regarding heterogeneous GPU/CPU compute.
In discussions with companies like Imagination, I am always curious how the needs in specific industry verticals influence requirements for the tools we provide. For hyperscalers, the best performance/power ratios are critical, combined with security. Colin added the perspective of "return per square foot" to the mix, which is about utilization and the energy needed.
As to workload utilization, I am impressed at how soundly Imagination pushes the aspects of virtualization, an area that a very hardware-centric EDA industry mostly sees only in emulation and FPGA-based and virtual prototyping. The requirements to achieve optimal workloads from the data center span hardware and software, and computing virtualization is critical. Thinking about how to handle the load balance of users with virtualized compute, combined with distribution information that reflects how the balance changes throughout the day. Generation Z and Alpha may be starting to consume local computing cycles right when the rest of us decide to sleep. And other parallel workloads can be balanced in, courtesy of virtualization. The industry needs to handle these challenges at the system level, where hardware and software are co-optimized.
For low power, we have long been collaborating to push the envelope for low-power design flows, one of the technology horizontals that Cadence is driving. I remember our discussions about dynamic power analysis that uses emulation-generated activity data to drive the lower-level implementation analysis (DPA) at the RT and gate level when the actual technology information in .lib files can be part of the equation. Flows like DPA increasingly find mainstream adoption, and collaborations like ours drive the requirements to develop the underlying tools. The trends are similar to utilization as in moving towards the system level, here extending from low power towards the aspects of thermal and EM analysis that extend well beyond the silicon.
Speaking of "moving beyond silicon," our discussion now shifts to domain-specific, workload-optimized design. Prof. Hennessy and Patterson dubbed this trend the "golden age" of semiconductors. When considering 3D-IC technologies in this context, for an IP provider like Imagination, customer discussions include the aspects of chiplet-based design. Do you deliver the IP as a chiplet? What interfaces need to be made available for die-to-die interconnecting? How are factors like "known good die" handled as the multiplication of probabilities coming from yield failures is a critical issue when disaggregating classic SoCs to assembly in packages? We agree that the area of heterogeneous integration is a traditional "it takes a village" situation in which no one player can handle this all by themselves. It takes a robust ecosystem of tool and IP providers with the assembly and technology providers. New alliances will be necessary here.
The Edge – Balancing Computing Between Consumer Devices and the Data Center
There is more to augmenting workloads in the data center and balancing computing. When mobile gaming users come online, one does not need a very powerful GPU in the data center. One GPU can sometimes service up to eight users in parallel, causing infrastructure changes optimized to more efficiently serve eight people on that single unit while not scaling the cost eight times. Again, virtualization is critical here. And the balance of computing is adapting to requirements. Sometimes the phone as an end device effectively acts as a screen and a second layer, linked to users' accounts as edge technology, resides inside 5G base stations. Colin cited some examples of growth, especially in Asia, that require special consideration allowing for the best user experiences that may include serving the proper advertisements at the right time, requiring different latencies. Based on the occasion, the industry optimizes consumer monetization based on the experience's scale.
With a focus on IP and tools, the Imagination/Cadence collaboration resides relatively low in the design chain. We compare notes on some of the requirements we hear from our customers, who ultimately decide what parts of computing are done on the device, far, middle, and near edges, and eventually in the data centers. Requirements propagate down from system companies and chip architects to us in the world of IP blocks and tools.
Consumers in different geographies pose different requirements, too. In areas—especially Asia—with the highest online rates, the majority of tasks are performed from phones. The balance of growth rates by geography has been changing and will likely shift further in the next couple of years.
Automotive – Data Centers on Wheels
Automotive is a critical area for both Cadence and Imagination. It imposes precise requirements on tools being "safe to use" per ISO 26262 and drives the need for tools to validate the functional safety of chips and systems. Last year, Cadence rolled out a comprehensive new safety planning and verification solution that addresses both digital and analog/mixed-signal aspects. Imagination comes to automotive from the graphics side, with a significant market share in infotainment. They have moved on to human machine interfaces (HMIs) in cockpits, replacing control buttons for windows, etc.
Autonomy is next with a mix of CPU and GPU. Imagination's traditional strong focus on safety and security helps growth in this area, as well as the combination with the ethernet packet processing products that support the proper automotive extensions. OEMs trust vendors' safety and security, not driving their custom components as in the case of ADAS. Imagination's presence of more than 15 years in automotive doesn't hurt here, either. The area of HMI is a very appropriate next step to take safety to that next level beyond infotainment. At 200 kilometers per hour, one needs to be able to trust all displays, and the hardware/software stack triggering wake-ups and safety mechanism at the right time needs to be safe and secure—or as Colin called it—"squeaky clean."
Looking at the generic block diagram of a high-performance compute architecture, it is clear that customers will choose IP from different places. It's an inverse "Lord of the Rings" situation. There cannot be only one IP provider that has it all, so in the era of competition of ecosystem players, different combinations of IP will evolve. Still, for companies like us, there are enough complementary areas to allow for a great collaboration.
We discussed the changes in the design chain in the automotive industry, which makes it so fascinating to be suppliers of IP and tools. Simply put, there are new customers as the OEMs take on a more central role and drive the development of their unique custom silicon as pioneered by new OEMs entering the market. In turn, addressing safety requirements during development across digital and analog mixed-signal domains is critical and a topic on which Imagination and Cadence have been working together for a while. In addition, the safety analysis in the front-end must connect to the implementation to guide which aspects require redundancy. The overall design flow becomes much more integrated. Implementation information flows back to the front-end for analysis, and the industry is progressing towards automated forwarding of requirements to digital implementation.
Another challenge in the design chain is the interaction of players. The availability of models of the IP has always been critical. Still, when integrating an SoC, as illustrated above, early software development relies on virtual provided by different vendors to work together. SystemC TLM 2.0 has become the standard to obey, and models have become an expected part of any IP offering. The balance of model fidelity and performance is more critical than ever, so users expect models for virtual prototyping and lesser accuracy but will also need models for hardware-based prototyping and emulation.
Colin had some interesting examples for software developers that cannot wait for silicon. IP providers like Imagination need to consider requirements from customers with many software developers with virtual prototypes that have an appropriate fidelity/performance balance for software decisions, architecture analyses, and software bring-up. Not everything can be done with hardware-based emulation. Doing this well before RTL is stable saves customers significant schedule time, addressing the needs of hundreds of developers. For mature IP blocks, customers consider RTL "sacred." Still, another important consideration is the ability to switch between development environments, and making a representative model available six months earlier certainly makes a switch worthwhile. The industry is quickly approaching ways to unify experiences like software debugging regardless of the underlying execution engine and fidelity.
Comparing notes on the complexity of the SoC block diagrams like the one above, another key topic we briefly touched on is interconnect, on-chip, off-chip, and between chiplets. There has been a lot of buzz in the industry around chiplet-to-chiplet interfaces, and complex on-chip interconnects that need to consider aspects like cache coherency for data access. For IP providers like Imagination, a certain level of neutrality is critical here. The IP interfaces are compatible with standard interfaces like AXI. For more complex considerations and aspects of connecting to HBM memories for instance, close cooperation with end customers yields a suitable solution quickly.
Finally, the changes in the automotive design chain have also increased the need for engineering talent—a key theme recently seen at the embedded world 2022 conference. One key solution is to make EDA more productive using AI/ML. Cadence Cerebrus technology for digital implementation delivers promising results here. Colin's team has been a teaching collaborator and customer for Cadence for a long time as they are pushing the envelope of requirements, and I am looking forward to a continued great collaboration.
This fascinating discussion with Colin re-affirmed the intricacies, complexities, and rapidly changing dependencies and responsibilities in the microelectronics ecosystem. No company can do it all, so collaborating is critical to solving customer challenges. We live in one of the most fascinating times for our industry ever, and I need to increase the frequency of catch-ups with Colin!