Signal and Power Integrity (PCB/IC Packaging) Blogs

This year’s CDNLive Silicon Valley user conference had more than 100 presentations from 12 different technical tracks. More than 20 exhibitors participated in the Designer Expo.

The customer paper on system-level PDN analysis methodology for an M.2 SSD of IC Packaging/Signal Integrity/Power Integrity track wins Best Presentation Awards and it was presented by Alex Tain from Seagate.

Alex opened his presentation with a review of PDN components and the frequency range effectiveness of different types of decoupling capacitors.

The list of inputs is given for a system-level analysis.

Alex then reviewed how PDN loop inductance is analyzed at chip, board, and decoupling capacitor locations to identify outliers and improve layout routing. His study found that ideally placed PCB decaps can be more effective than non-ideal IC package decaps.

Then the optimization workflow and its options were reviewed along with the decoupling capacitor library.

Alex also explained how their target-impedance constraint was achieved with decoupling capacitor optimization that also minimized product cost. The system level optimization shows that the IC package decoupling capacitors could be completely removed.

To review and download Alex Tain’s presentation, click the image below.

Thanks to Alex Tain, and all the other contributors to CDNLive SV 2018. It was a lively and highly educational conference.

Team Sigrity