Signal and Power Integrity (PCB/IC Packaging) Blogs

Exposing Adaptive EQ in 32 Gbps Receivers

It is no secret that serial link data rates have skyrocketed over the past 15 years or so. What was considered cutting edge back then in the 2.5 – 3.25 Gbps range now appears in stark contrast to the 112Gbps PAM4 technology we see today. Yet there are some common threads that appear throughout the relentless march to increase bandwidth. From about 8Gbps onwards, adaptive equalization (EQ) in receivers has been a key enabler to opening up eye diagrams and meeting signal integrity requirements. This initially showed up as decision feedback equalization (DFE) became commonplace in receivers and has since expanded in adaptive Automatic Gain Control (AGC, a.k.a. variable gain control or “VGA”) and continuous time linear equalization, or CTLE. When these different types of EQ exist in the same receiver, adapt independently, and handshake with each other to produce the final result, things get a little more complicated. Even transmitters get into the adaptive EQ act, where backchannel training enables the receiver to advise the transmitter on how to tune its feed forward EQ, or “FFE”.

In January this year at DesignCon (DesignCon 2019), Greg Edlund from IBM presented a session called “Exposing Adaptive EQ in 32 Gbps Receivers”, which covered a lot of this material, using 32 Gbps PCI Express 5.0 functionality as a baseline. This session covered the usage of IBIS-AMI models that employ adaptive EQ techniques, the interplay between different types of EQ co-adapting real time, some of their limitations, as well as new uses for these types of models and the simulations you can perform with them. To see the complete presentation, please click here.

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