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In modern electronic systems, there may be tens to hundreds of DC rail voltages used in the system, with voltage levels, for example, ranging from 48V/24V to 3.3V, 1.8V, 1.2V and even as low as 0.8V. Usually these systems will have a few input DC rail voltages and then are converted to other DC voltages with DC-DC converters and Low Drop-Out (LDO) regulators. Since hundreds of DC voltage rails may exist in one system or even on one PCB, Power Integrity (PI) engineers need a way to visualize the entire power topology and assure the DC IR drops and AC voltage ripples of the system’s Power Delivery Network (PDN) meet the requirements of the active component loads.
Enter Cadence’s PowerTree technology; this utility goes well beyond the simple task of visualization of the PDN to enabling a team-based approach to Power Integrity analysis and reducing overall design time to market. The PowerTree tool uses the schematic netlist to easily generate the tree. Component data can be entered through the Analysis Model Manager (AMM) to allow pre-layout simulation of the PDN for setting PCB layout requirements and component selection. PowerTree stores all the PDN setup including source/sink definitions, component models, net names, decoupling capacitor values, and target impedance constraints among other information making it fast and easy to run PI analysis in either the Sigrity PowerDC tool or the Sigrity OptimizePI tool. Moreover, the tree data can be modified and reused as needed in other designs to further reduce your design cycle time.
Recently Google and Cadence jointly presented new functions in PowerTree such as Multi-level Tree topologies and DC-DC/LDO/Load switch models at DesignCon2019, you can read/download the paper in the below link. The presentation also discusses 10X improvement in total setup time using PowerTree for PowerDC simulations.
As an example, the following PowerTree provides a high level picture of the entire power topology from the system power source in a PCB system:
The hierarchical structure gives a block level view of a multi-level tree topology for the entire power system. Each green block has a specific voltage rail topology.
With the AMM, IC component thermal models can be assigned to PowerDC through PowerTree:
This dramatically reduces the setup time for electrical/thermal co-simulation of a complicated PCB layout.
With the thermal aware DC analysis, you will get accurate IR drop and temperature distributions for your PCB system.
For more information about electrical-thermal simulations, check out our PowerDC page. Also, take a look at our white paper on “How a Team-Based Approach to PCB Power Integrity Analysis Yields Better Results”.