Signal and Power Integrity (PCB/IC Packaging) Blogs

Cadence will kick off this year’s CDNLive worldwide user conference series starting with Silicon Valley on April 2-3 at the Santa Clara Convention Center in Santa Clara, California.

The keynote presentations begin at 10:30 a.m. and will include presentations from industry leaders and visionaries who influence the global electronics marketplace. The discussion will include trends in systems, silicon, and applications and speakers will share their thoughts on the challenges and opportunities that face the engineering community today.  You are highly encouraged to attend and learn about exciting new developments.

Also, please join us at the SI/PI and IC Packaging track (Room 205);

The track will highlight Cadence users that have overcome challenges in Signal Integrity, Power Integrity, interconnect extraction, and more.  You will have the chance to hear from companies like Intel, GLOBALFOUNDRIES, and Samsung as they share their approaches in using simulation tools to build cost-effective and reliable products efficiently.

The full agenda of the SI/PI and IC Packaging track:

• Tuesday, April 02

(click for full image)

• Wednesday, April 03

(click for full image)

You also won’t want to miss our demonstration at the Designer Expo:

• Thermal-aware PI design and analysis including multi-level tree topology set-up from PCB schematics
• Power-aware SI analysis of next-generation GDDR and LPDDR interfaces using IBIS-AMI models
• Streamlining multi-gigabit SI and 3D interconnect extraction across PCB-connector interfaces for TX-to-RX interface compliance

For a complete agenda and registration, view the event page.

You could also download the CDNLive APP at the apple store to get the event agenda and mark your interested presentation topics so that you won’t miss them.

For more details, please join us on Apr. 2-3 at the Santa Clara Convention Center.

We look forward to seeing you soon at CDNLive Silicon Valley 2019!

Team Sigrity