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As data rates for serial link interfaces such as PCI Express® (PCIe®) Gen 4 move into the double-digit gigabit transfer rates, device modeling, interconnect modeling, and analysis methodologies must continue to evolve to address the shrinking design margins and increasingly challenging compliance criteria facing today’s engineers. To mitigate risk and optimize designs, it is critical to move analysis as far upstream as possible to enable trade-offs, feasibility studies, component selection, and constraint capture.
Accurate modeling of SerDes transmitter and receiver equalization in the link are paramount to obtaining realistic simulation results, including the complex adaptive equalization that is present in nearly all high data rate serial links. Interconnect modeling also faces new challenges with via arrays requiring full wave 3D solutions in order to accurately characterize their complex via stub and coupling behavior, threatening to drive extraction times from minutes to hours or days. After simulation, interface-specific post-processing is often required to check transmitter, channel, and receiver compliance criteria.
This blog series will suggest methodologies for creating a “virtual prototype” of your serial link pre-design, and how to create the associated interconnect and SerDes models that go with it. We will review how to utilize IBIS-AMI models, and how to build your own if they are not available when you need them. It will also show you the latest interconnect extraction techniques to give you “full wave accuracy where you need it” while keeping computational times in control, and how to use standards-based compliance kits to automate post-layout analysis and signoff for advanced interfaces like PCI Express Gen 4.
As data rates continue to accelerate and supply voltages continue to shrink, the “unit interval”, or “UI” with which to interpret logic has compressed significantly.
Figure 1 – Various PCI Express data rates running through 8” of FR4 stripline
With less and less margin to work with, it becomes increasingly important to move the signal integrity (SI) analysis process further upstream, to address issues and challenges earlier in the design process, allowing mitigation of risk at the back end of the process. This requires some shifts from traditional methodologies, as well as new techniques for modeling the serializer/deserializer, or “SerDes” devices that transmit and receive our high speed signals. The fruit of this up-front labor is an optimized Bill of Materials (BOM) for the design, as well as constraints to enable a constraint-driven printed circuit board (PCB) physical layout process. Combined with efficient post-layout interconnect extraction and automated compliance checking, the goal is to be able to confidently sign off your design to fabrication, without major surprises or schedule impacts, and achieve success with your hardware, all while avoiding costly and time-consuming re-spins.
One key element to a successful methodology for interfaces at these data rates is to move the SI starting point significantly upstream of the traditional post-layout verification step. There is a false notion that meaningful analysis cannot be performed until after detailed PCB layout is done, in a traditional “bottoms-up” methodology. Reality in a hardware design environment is actually quite different.
When the layout designer has completed their layout, there is typically a short time period of a day or two where engineers from the various disciplines (mechanical, thermal, signal integrity, power integrity, EMI) may get a chance to do a final review and provide some last minute inputs on the layout. But there will typically be considerable pressure from the project manager to release Gerbers to the PCB fabricator within a specified time slot, the assembly house will be lined up to order components and receive those bare boards for assembly and test, and the software engineers will be waiting for hardware to come into the lab so they can try out their latest software versions. In other words, a full Domino effect of supply chain dependencies will be captured in the project manager’s Gantt chart by the time PCB layout is initially completed, and the time available to perform detailed SI analysis at that point will be short. It is often more likely that you will “run analysis until you run out of time, then ship” as opposed to “run analysis until you are satisfied the interface will work, then ship.”
In order to accomplish a confident signoff for your critical interface in the compressed back-end of this PCB design process, preparation is critical. One strategy is to go “top down”, and build an early version of a simulation test-bench of your serial link interface, well in advance of that late stage. This can start upstream of a detailed schematic capture, at the early BOM stage, when you get an initial understanding of the SerDes and protocol (ex. PCI Express Gen 4) that will be used to transmit and receive signals, a general idea of the partitioning of the system, how many PCBs will constitute the signal path, and what connectors will likely be used. Detailed models for all the blocks in the system are not critical at this early stage, and “placeholders” can be used initially, with the understanding that they will be replaced later as more detail becomes available. (Compliance kits are a rich source of preliminary models for your early test-bench, and will be covered later in this blog.) In a nutshell, if you can draw the interface on a napkin, you should be able to put together an early simulation test-bench. The benefits to this kind of top-down methodology are multiple:
Figure 2 – General design methodology
With an initial prototype of your serial link topology in place, and at least placeholder models assigned to the various blocks, you should have a test-bench that simulates, and passes traffic at the targeted data rate. Now the work begins to replace models with more detailed, more realistic models as you go through the design process. These models generally fall into one of several general categories:
The first step is to do a gap analysis between the models you need for the various blocks in the topology, and the models you have on hand in your library. Augment your test-bench with the models that you have, and verify that they simulate cleanly. Next, make list of the models that are missing, contact the model supplier (can be internal or external), and put in requests for the models that you need. Keep track of who you had contact with, the dates of contact, and the status of the model. As you get them, augment your test-bench accordingly.
Next time > Pre-Layout Modeling of PCB Interconnect
Ken Willis is a Product Engineering Architect focusing on SI solutions at Cadence Design Systems. He has nearly 30 years of experience in the modeling, analysis, design, and fabrication of high-speed digital circuits. Prior to Cadence, Ken held engineering, technical marketing, and management positions with the Tyco Printed Circuit Group, Compaq Computers, Sirocco Systems, Sycamore Networks, and Sigrity.
More about Signal Integrity:
How to Address the Challenges of Serial Link Design and Analysis
Why SerDes Signaling Is Trending Towards PAM Encoded Signals
How to Build an IBIS-AMI Model (Video)