Signal and Power Integrity (PCB/IC Packaging) Blogs

System designers are familiar with standard DDR4 RAM components but with the demands on increasing performance and decreasing power consumption in mobile products, LPDDR4 and its variation, LPDDR4X, have become the desired memory devices for in-vehicle infotainment, smartphones, tablets, and thin notebooks. Understanding the design specifications for LPDDR4 and LPDDR4X devices and their application conditions is critical to achieving successful system-level designs.

Like DDR4 memory requirements, the performance of LPDDR4 is measured by eye mask, jitter, and BER.  In addition, LPDDR4 and 4X interfaces specify these measurements to both the data and address signals, with LPDDR4X operating at the I/O supply voltage reduced by 55%.

When evaluating and implementing a DDR4/LPDDR4/LPDDR4X interface in a system, designers face additional challenges in modeling and analyzing the memory subsystem besides the normal Signal Integrity (SI) and Power Integrity (PI) considerations. For example, BER measurements using serial link analysis techniques can only be achieved on individual channels of differential signals. For memory applications with parallel bus groups of single-ended signals, directly applying the channel analysis method is not enough and new methodologies need to be in place to guide design practice.

In this year’s DesignCon (DesignCon2019), a group of engineers at Texas Instruments shared their experience in designing and analyzing LPDDR4X interfaces in their products. Their solutions and discussions are invaluable to system designers who are looking to understand common design concerns regarding LPDDR4X:

1. How to handle the memory controller’s requirements for the READ cycle? Memory controllers today, such as the ones provided by the Cadence IP division, are equipped with advanced features that can help with troublesome timing parameters.
2. When applying the channel simulation method to parallel bus simulations (to meet the BER specification of LPDDR4X), designers need to understand the interconnect response in a serial link channel is different from a group of bus signals. Validating the channel simulator and circuit simulator is a necessary step in the analysis process.
3. The biggest challenge for designers is how to proceed with a correct simulation methodology for high data rate buses. With the JEDEC specification being so complicated and many design rules/guidelines to follow, it can be a nightmare for designers to evaluate their designs and generate a DDRx measurement report. Fortunately, using Cadence provided simulation templates for data (including WRITE and READ) and address signals of LPDDR4X, designers can follow a step by step analysis process, to perform complete design analysis without missing important noise effects, such as crosstalk and power supply noises.

For the details of TI’s LPDDR4 design success, visit here.

Team Sigrity

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Further Reading

• Blog: Power-Aware SI DDR4 Simulation: You Have a Choice!
• Blog: Chiplets -- Reinventing Systems Design
• LPDDR4 Complete Solution