Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I want to do a HAL analysis on VHDL design.What are the procedure and steps for that?/
Please tell me
If you compile your design with "irun" already then you can just add the "-hal" switch, then use the "ncbrowse" tool to review the lint messages via a GUI.
Alternatively if you use ncvhdl/ncelab/ncsim, then after elaboration you can invoke "hal" and pass the snapshot name on the command line to HAL.
In reply to StephenH:
apply command "nclaunch"
select a design
select all vhd files in selcted design and press ncvhdl option .
After this it give various errors .. How to resolve that?
How to elaborate particlar design?
In reply to sonam20:
How to get sanpshot of elaborated design.??
Without seeing your compilation log there is no way to know what those VHDL errors are, nor can we guide you to resolve those unknown errors. I would recommend talking to one of your colleagues to get the required compilation order for the files, as well as any specific switches like VHDL-93 options etc.
Alternatvely you could post the log file here, or go to http://support.cadence.com/ and file a service request asking for help to run HAL.
I found these type of error after compilation. Please tell me how to resolve them.
ncvhdl_p: *E,LIBNOM (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,35|18): logical library name must be mapped to design library [11.2].USE DESIGN.BB_PKG.All; |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,38|9): identifier (DESIGN) is not declared [10.3].USE DESIGN.WB_INTERNAL_PKG.ALL; |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,39|9): identifier (DESIGN) is not declared [10.3].USE DESIGN.COMMON_PKG.ALL; |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,40|9): identifier (DESIGN) is not declared [10.3]. P_SLAVE_BASE_ADDR : slave_addr_a_t(0 TO P_NUM_SLAVES-1) := (((x"0000"),(x"0280"),(x"0000")), --! Specifies base address of each slaves |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,48|37): identifier (SLAVE_ADDR_A_T) is not declared [10.3]. P_SLAVE_ADDR_SIZE : slave_addr_a_t(0 TO P_NUM_SLAVES-1) := (((x"007f"),(x"027f"),(x"0000")), --! Specifies the address size of each slave |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,52|37): identifier (SLAVE_ADDR_A_T) is not declared [10.3]. P_SLAVE_ADDR_CH : slave_addr_ch_a_t(0 TO P_NUM_SLAVES-1) := (('1','1','0'), --! Specifies the active address part of each slave |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,56|40): identifier (SLAVE_ADDR_CH_A_T) is not declared [10.3]. P_SHARE_PRIO : int_vector(0 TO P_NUM_MASTERS-1) := (1,2,3,4,5) --! Priority of master |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,60|33): identifier (INT_VECTOR) is not declared [10.3]. wbm_i : OUT wbm_i_a_type(0 TO P_NUM_MASTERS-1); --! Wishbone master input interface array |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,71|33): identifier (WBM_I_A_TYPE) is not declared [10.3]. wbm_o : IN wbm_o_a_type(0 TO P_NUM_MASTERS-1); --! Wishbone master output interface array |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,72|33): identifier (WBM_O_A_TYPE) is not declared [10.3]. wbs_o : IN wbs_o_a_type(0 TO P_NUM_SLAVES-1); --! Wishbone slave output interface array |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,76|33): identifier (WBS_O_A_TYPE) is not declared [10.3]. wbs_i : OUT wbs_i_a_type(0 TO P_NUM_SLAVES-1) --! Wishbone slave input interface array |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,77|33): identifier (WBS_I_A_TYPE) is not declared [10.3].ARCHITECTURE rtl OF intercon IS |ncvhdl_p: *E,ENNOFN (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,82|27): Intermediate file for entity 'INTERCON' could not be loaded, entity may require re-analysis.LIBRARY design; |ncvhdl_p: *E,LIBNOM (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,39|13): logical library name must be mapped to design library [11.2].USE design.bb_pkg.ALL; |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,40|9): identifier (DESIGN) is not declared [10.3].USE design.common_pkg.ALL; |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,41|9): identifier (DESIGN) is not declared [10.3]. dm_in : IN dm_in_a_t(0 TO P_NUM_REG_MAP-1); --! Number of elements = no. of register maps |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,50|31): identifier (DM_IN_A_T) is not declared [10.3]. reg_wbs_i : IN wbs_i_type; |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,54|33): identifier (WBS_I_TYPE) is not declared [10.3]. dm_out : OUT dm_out_t; |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,58|32): identifier (DM_OUT_T) is not declared [10.3]. reg_wbs_o : OUT wbs_o_type |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,62|33): identifier (WBS_O_TYPE) is not declared [10.3].ARCHITECTURE rtl OF wb_dm_bridge IS |ncvhdl_p: *E,ENNOFN (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,68|31): Intermediate file for entity 'WB_DM_BRIDGE' could not be loaded, entity may require re-analysis. Concatenation: FOR i IN P_NUM_REG_MAP DOWNTO 1 GENERATE BEGIN |ncvhdl_p: *E,EXPEND (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,83|58): expecting the reserved word 'END' [9.7].END ARCHITECTURE rtl; |ncvhdl_p: *E,OPARCH (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,134|15): Optional end architecture is only allowed in 93[1.2].ncvhdl_p: Memory Usage - 8.4M program + 4.9M data = 13.2M totalncvhdl: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.1s, 24.0% cpu)
You can use cadence quick help for more explanation: nchelp ncvhdl_p LIBNOM
The logical library name indicated is not mapped to a design library.
Section [11.2] of LRM [87 & 93]. A user option file entry of the form:
must be present for each logical library name L.
ncvhdl_p: *E,LIBNOM (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,35|18): logical library name must be mapped to design library [11.2].USE DESIGN.BB_PKG.All; |ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,38|9): identifier (DESIGN) is not declared [10.3].
This message, which seems to be the cause of most of the following error messages, is saying that the parser doesn't know where to look to find the compiled objects for the BB_PKG package. It doesn't know where the library called "DESIGN" was stored.
Cadence tools use a file called "cds.lib" to map logical library names to physical disk locations. Search for "cds.lib" in the NCLaunch documentation for help in setting up that mapping file.