Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I suspect you are encountering a zero-delay loop race condition in the code. When the -access option is used, under the hood the result is the turning off of optimizations designed to have the simulator perform as efficiently as possible. When optimizations are enabled/disabled the result can be a reordering of events within the various time slices. In a race-free design this reordering will have no effect on the result of the simulation. If there are races in the design, however this reordering can and often does highlight situations in the code that are dependent on a certain evaluation order to produce the desired simulation effects. Because different simulators use different algorithms to process events, changing from one simulator to another can also highlight code that is dependent on a given evaluation order.
How to find the race? That's really the million dollar question. Unfortunately it's not always easy. One method would be to add "+nclinedebug +gui" to your command line to bring up the simulation in an interactive gui. Bring up the source browser and hit the play button and take note of the increasing time and delta cycles. When you note that time has stopped and only delta cycles are increasing you know that you have encountered the zero-delay loop. Thereafter hit the pause/play button until you can determine the section that code that is getting updated and reupdated during the loop.
Hope that helps.
Hello Jack and Mike,
I am facing the same problem as yours and I am using Synopsys's STIL Direct Pattern Validation flow, which means I am taking the patterns generated by Tetramax and simulating using NCSIM and having that same hanging issue. My problem is that I can not disable access since it is used by PLI routins to force values during simulations. Is there any other way of getting rid of that haning issue other than disabling access?