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I'm facing a problem with assura 3.1.4 in the LVS. Independentely on the kind of circuit i run, the DRC works according to the design rules of my technology, while the LVS systematically fails with this error message (example of a simple inverter http://postimage.org/image/e8qzr6zxr/ ):
Loading umc13mmrf/libInitCustomExit.il ... done!
Loaded umc13mmrf/libInit.il successfully!
*WARNING* Cannot find /cadence/ASSURA/tools.lnx86/dfII/etc/tools/layoutXL directory to load environment variables
Assura LVS of UMC 0.13um Mixed-Mode and RFCMOS 1P8M MMC FSG Enhancement Process (Ps: Pls select the switches of metal opton and metal combination !! )
error: Unknown input 'incremental' found in this geomConnect() command.
629. geomConnect(incremental (buttOrOver ME2 MESH_SY_P1_CONN) (buttOrOver ME3 MESH_SY_P1_CONN) (buttOrOver ME2 MESH_SY_M1_CONN) (buttOrOver ME3 MESH_SY_M1_CONN) (buttOrOver ME2 MESH_SY_P2_CONN) (buttOrOver ME3 MESH_SY_P2_CONN) (buttOrOver ME2 MESH_SY_M2_CONN) (buttOrOver ME3 MESH_SY_M2_CONN) (buttOrOver ME2 MESH_ASY_P1_CONN) (buttOrOver ME3 MESH_ASY_P1_CONN) (buttOrOver ME2 MESH_ASY_M1_CONN) (buttOrOver ME3 MESH_ASY_M1_CONN) (buttOrOver ME2 MESH_ASY_P2_CONN) (buttOrOver ME3 MESH_ASY_P2_CONN) (buttOrOver ME2 MESH_ASY_M2_CONN) (buttOrOver ME3 MESH_ASY_M2_CONN) (buttOrOver MESH_SY_P1_CONN MESH_SY_P1) (buttOrOver MESH_SY_M1_CONN MESH_SY_M1) (buttOrOver MESH_SY_P2_CONN MESH_SY_P2) (buttOrOver MESH_SY_M2_CONN MESH_SY_M2) (buttOrOver MESH_ASY_P1_CONN MESH_ASY_P1) (buttOrOver MESH_ASY_M1_CONN MESH_ASY_M1) (buttOrOver MESH_ASY_P2_CONN MESH_ASY_P2) (buttOrOver MESH_ASY_M2_CONN MESH_ASY_M2) (buttOrOver ME2 MOM2_term_P) (buttOrOver ME2 MOM2_term_M) (buttOrOver ME2 VP3_ME2_1) (buttOrOver ME3 VP3_ME3_1) (buttOrOver ME3 VP3_ME3_2) (buttOrOver ME4 VP3_ME4_2) (buttOrOver ME4 VP3_ME4_3) (buttOrOver ME5 VP3_ME5_3) (buttOrOver ME5 VP3_ME5_4) (buttOrOver ME6 VP3_ME6_4) (buttOrOver ME2 VP4_ME2_1) (buttOrOver ME3 VP4_ME3_1) (buttOrOver ME3 VP4_ME3_2) (buttOrOver ME4 VP4_ME4_2) (buttOrOver ME4 VP4_ME4_3) (buttOrOver ME5 VP4_ME5_3) (buttOrOver ME5 VP4_ME5_4) (buttOrOver ME6 VP4_ME6_4))
630. geomConnect(incremental (svia TMV_RDL AL_RDL ME8 MMCTP MMCBP))
error: Layer 'ptap_p' is not connected.
632. geomStamp(PWBLK ptap_p)
error: Layer 'ptap' is not connected.
633. geomStamp(PSUB ptap)
error: Layer 'ntap' is not connected.
634. geomStamp(wel ntap)
error: Layer 'ttap' is not connected.
635. geomStamp(TWEL ttap)
error: Layer 'ptap_all' is not connected.
636. geomStamp(PSUB_P ptap_all)
error: Connected input layer 'ptap' is expected.
Abnormal termination at Mon Jun 4 11:16:42 2012
intermediate: 1.15dt 1dw 1.21t 49.1meg 0pf 0.0rss 0r 0w
errno: 0, code: 1
*ERROR* Segmentation violation - run abnormally terminated
File avtsignal.c, line 80, stack:
*WARNING* Translation abnormally terminated!
***** aveng fork terminated abnormally *****
*WARNING* /cadence/ASSURA/tools/assura/bin/aveng exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated
I can't figure out what's going wrong , i hope anyone can help me.
Thanks in advance,
Sorry, I posted in the wrong section. Now refer to custom IC design.