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Sorry that you are seeing a crash. We continuosly strive towards making the CtoS more robust and appreciate any help we can get from customers.
You are probably predicted what I am going to ask next: Would it be possible for you to contact Cadence customer support so that someone can work with you?
If that is not an option, here are some tips:
- Does your design pass simulation? Do you have a good SystemC (or any other language) TB to verify your DUT (design under test)? You can catch a lot of coding errors during simulation. You would be surprised how many customers simply write the SystemC DUT, don't simulate at the SystemC level, generate RTL from CtoS and do full simulation at the RTL level... IMO, those people are missing the point. You want to do all functional verification at the SystemC (high-level) and re-use the high level TB to verify the generated RTL.
- Run with 'build -verbose'. It will print debug messages as it parses your design. You might be able to figure out which line it is having a problem with.
NOTE: Please post all your future TLM-D (CtoS) questions to:
High Level Synthesis Forum