I'm trying to simulate a practice code . Verilog verification of my code do not give any error.But when I try to elaborate, this error is being showed:
ncelab: *E,CUVHNF (./FSM_test.v,17|20): Hierarchical name component lookup failed at 'l'
What does this mean? How can I debug this error ? Is there any archive or list of possible error list so that I don't have to ask in forum to understand the errors.
This error is saying that you have used a hierarchical name in your Verilog source code. But the elaborator can't find the signal or module 'I' that you have included in that hierarchical name.
To learn more about what errors mean, use the "nchelp" utility. It takes as arguments the tool issuing the error message and the error message code itself.
> nchelp ncelab CUVHNF