Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I am not able to back annotate to my dsn file.While back annotating one pin(power pin) is showing error and i m getting this error. Pls help me.
#520 ERROR(SPCODD-520): FUNC_LOGICAL_PATH must be specified in line 3736 of pinView.dat
ERROR(SPCODD-521): Cannot process pin R1 on pkg U11 connected to net.
ERROR(SPCODD-507): Physical net name: VCC_1V8_DDR
#1 Error [ALG0037] Unable to read physical netlist data.
#2 Aborting Swap file creation... Please correct the above errors and retry.
May be this net name is not present or renamed in your design. And check the component whether it renamed before you start backannotation
In reply to C Shiva:
Hi siva ,
thank u for ur reply.
I chked with the design. The part ref has changed in the pcb, and there are many other pins to which the same net is connected. and still i m getting the same error info.
In reply to souparnika:
Can you attach the error list in text file. I will try to find...
Since you're in OrCAD it sounds like you changed the schematic and then attempted the backannotation. This is not possible because the packager will get out of sync. You might be successful if you go back and make the schematic match the board at the last forward annotation --- or manually fix the problem and make sure it does not happen again. :)
In reply to redwire:
Redwire is correct. Please check as per his instruction.
In the error list while importing schematics "No_connect" property found. But as per my experience, i also got same warnings many times, but didn't get any problem in board file. I think this is ignorable. What's your opinion?
The "No Connect" warning can be ignored. What typically happens is that an engineer places a "no connect" symbol on a pin (which will alleviate DRC errors, and then later connects a net to the pin. The "no connect" symbol disappears on the schematic page but the netlister still sees it telling you it's hiding underneath. I always ignore those errors unless I am bored. :)
Thanks redwire. I felt it as same. It is hiding underneath the pin. We can see it by double clicking on the pin.
Have a nice day... :-)
hi ,i met the same question and did't know how to find the source of the problem.
when i tried to backannotation ,it always occured the following errors :
#549 ERROR(SPCODD-549): No physical part found for COMP_DEVICE_TYPE=EP2C70F896_4_BGA896_EP2C70F896, regenerate the netlist to sync with Allegro board. ERROR(SPCODD-516): Line Number: 13#1 Error [ALG0037] Unable to read physical netlist data.#2 Aborting Swap file creation... Please correct the above errors and retry.