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I don't see why an external gerber tool won't see the physical connection using your original method. If the ADD_ETCH layer is part of the film control for the layer you want the connection on, it should show up in your gerber.
If you go to static shapes and get a DRC, you can Waive it or use the NET_SHORT property to get rid of the DRC.
In reply to Randy R:
I can see it on an external gerb tool. My supervisor hasn't seen this method before and I'm having a heck of a time convincing him this method works. He is of the school "if I can't see a physical connection, it's not there". As long as I'm okay with the static shapes, I think I'll go that way.
I personally do not allow this method in my company. If the net name is different it is not allowed to connect unless an "alias" (from Concept) body is placed on it or it has a secondary name (OrCAD). Either method reduces the net to one physical net in the board and the IPC netlist works.
Your method sounds like you're trying to fix something in the layout that has an elegant solution back at the schematic.
Kudos to your boss. :)
In reply to redwire:
In reply to Goblin59:
I fully agree with redwire: the solution IS at schematic level.
I do not allow to do some "strange" manipulation for this kind of requirement... so dangerous
In reply to jch teyssier:
My company currently uses a device similar to what Ron described: a multi-pin schematic symbol and a PCB footprint, with matching numbers of pins, to which multiple nets are connected. During artwork creation, a subclass which has lines across the pins of this device is merged with the copper to short across the pins. I'd like to go to a different method of shorting nets for the reasons given above.
The good thing about this method is that the engineer can choose the location at which nets short. This is imperative.
In Concept/DEHDL, I can't use global net shorts because I have no control over the location of net short. And I can't use an ALIAS because I most often use this for power and ground nets, which are global. Or maybe one of these methods will work, and I'm just not using it properly??
I have added the NET_SHORT property to a pin on a schematic symbol, but that property doesn't get passed to the footprint pin. Using this property seems somewhat archaic if one has to manually enter the net names anyway - I'd hope I could click on some nets to create this property's value or at least select from a list of nets.
Is there a way to short nets, global or not, in such a way that the location of the short on the PCB can be chosen by the user?
In reply to EvanShultz:
If you are using HDL can you not add a component (net_short) that has x_number of pins (depending on the number of shorts). Make the footprint a via and place all the pins on top of each other. Once the netlist is imported you will have to add some properties to the pins - NET_SHORT and to the symbol NODRC_SAME_SYM_PIN. But at least your net short will be in a pre-defined location.
I have attached a pdf file that shows this principle working except that the front end tool is Capture and the net short property can be defined in Capture and transfered to PCB.
In reply to steve:
EvanShultz comment hit the nail on the head:
Is there a way to short nets, global or not, in such a way that the
location of the short on the PCB can be chosen by the user?I am not sure how dangerous this would be but may be the tool should support NET_SHORT property such that it can be applied to nets and when done so, the tool will allow two differently named nets to be connected without giving Line to Line spacing error. Of couse, utmost precaution will be required...
I think v16.3 added jumper support but not sure if that applies in this situation.
In reply to Khurana:
I'm not sure where I was failing before. After reading some links I found by searching "net_short" in COS and playing around a bit, I was able to implement NET_SHORT either from the schematic or the board. My demo project was quick and simple, thus omitting hierarchical blocks and other project bits that might ultimately end up causing problems. I'm going to play more...
Place any single-pin comp on the schematic and connect it to some net. Then click on the pin (not the comp body!), which lights up a flashing red box around the pin for me, and open the Attributes form. Add a new prop to the pin, name it NET_SHORT, and put the nets, separated by a colon, as the prop value. Without having to specifically set up this property to transfer in PXL, but with "Create user-defined properties" checked on the Export Physical form (which I always check), the prop shows up on pins in Allegro.
Imagine the pin has "direct" connection to NET1 and the prop is NET_SHORT=NET1:NET2. Routing to NET1 is like normal. But when I route NET2 to the pin, it doesn't want to add the connection because a DRC error is being created. But if I pick Done from the RMB menu, I believe the DRC error is being suppressed.
This does in fact work, but it's not exactly intuitive since the "additional" Clines don't really want to join the pin, you can to make them. Furthermore, adding the prop to the schematic pin by hand is archaic.
I can simply connect a single-pin comp to any single net and run PXL. In Allegro, I manually add the same prop to the pin. In this case, again, routing the "direct" Cline is easy but I still get a DRC error when I drop in the "additional" Clines. Until I noticed that I must avoid bringing the "additional" Clines to the origin of the pin and just end them somewhere within the area of the pad. Also, I can't route from the pin with the NET_SHORT property because the Cline will then get a "Dummy net" connection and I can't create connectivity with elements of the "additional" net. Shapes are easy.
I could rip out a PCB SKILL program to easily allow users to select nets and apply this property, maybe even with some intelligence to assist users or auto-pick for them. So that's a possible plus, although I think I need to ponder how a tool for doing this with a GUI could be best used. Since Concept SKILL doesn't support native forms, it's far more difficult to try something similar on the front end, where it belongs.
So again, it works. But I still have to manually type in the net names (but not the property). And I have to route towards the pin with the NET_SHORT property and be careful to end the Cline on some random spot within the finish pad area. Plus there's no schematic annotation of shorted nets
Either method has serious drawbacks. I can understand why this was a User Group Top 10 request as stated by Solution ID 1835116, but I'd bet the user group had a less clumsy implementation in mind.
Please, someone tell me I've still got it wrong and there's a sensible way to short nets at a specific point on the board.
I have been trying to get this to work for us and eliminate any OFE (opportunity for error), the ability to see if the short is made at the logical view, ability to make sure the short was routed in the report (Summary Drawing Report), able to export to AnsoftLinks and able to provide DRC checking to non shorted nets. This is what I have done so far:
I created a 2 pin component consisting of simple round single layer pads and placed them on top of one another. We use SCM for our front end so when the component is added I add the NET_SHORT property to each pin and attach the appropriate values (AGND:GND and GND:AGND). Export Physical to my SiP design and when the component is placed there were no Pin to Pin Drc's and I have a rats nest showing, so far so good.
I can route into the pins from either net with no problems but I get a Line to Line DRC. Ideally we would like to have this "Net Short Component" placed and connected by over lapping shapes so the geometry can easily be modified to accomodate the particular layout (i.e. small connection for some and large areas for High Voltage designs). When I place the component and bring a shape over it from the 2 different nets I get Shape to Shape DRC's. I used the SHORTING_SCHEME property on the 2 different nets assuming this would eliminate my DRC's but that has not worked either.
This appears to be so close to working but I am not able to eliminate the DRC. Our company is regulated by FDA so we have to document each and every DRC in our designs so obviously we strive to have no "flase DRC's" within our designs.
Froom what I am reading in the Help files it would appear the NET_SHORT property would work by itself but since it did not it appeared to be logical to try the SHORTING_SCHEME in addition to the NET_SHORT but again that is not working.
Has anyone have this working with the requirements I have listed in my opening paragraph?
In reply to tonyhuffman:
Well the SHORTING_SCHEME property did not bring anything to the party so I am still puzzled. Any ideas?
Hello Ron, I have seen what you are trying to do before. On my end of things as I do RF boards things like transmission line stubs that need to be grounded at on end or shorted to ground can be a problem unless I have a real footprint for the actual transmission line.
I think it is really best to not "Hack it" if at all possible. Your schematic from a net perspective should match the board. I agree with your boss in that he does not want to allow it.
If that board ever needs an ECO I think it is highly possible that things might go bad and a board may come back without the short.
Now you could directly edit the gerber files before you send them out to the board house. I would not have the board house make any changes to the gerbers, thats kind of playing with fire.
I have to think fabricators are calling with questions (and putting
the job on hold) when shorted nets aren't specified in the fab drawing
If you design power systems with force/sense lines, it is faster/safer to check the sense location if the short is a physical component. ATE testing of a 120-pin PMIC device with 16-30 different regulators for portable devices has lots of sense lines. Ultimately, deliberate shorts have to be visible, controlled, and verified on the schematic/netlist level.
MGCDesignArchitect has a "net alias" function allowing you to connect two nets together. But, which net will get exported to layout as the other netname never leaves the schematic causes extra work (schematic pages are compiled in numerical order. Net name assignment isn't random. But, it may as well be.) Engineers have no easy way of finding where the designer put the sense line junction on a power net.
Our default template for fabrication drawings specifies merging short artwork after cam DRCs to copper artwork. It works for us. Our design review process focuses on a DRC report with zero errors, zero override.
If we have to, we'll list the shorted nets on the fab drawing.