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Does anyone have any suggestions on creating footprint with thermal pad that requires topside via tenting on the top side?
I tried making shape symbols for solder mask/ paste mask, but due to the void in the shape it requires I am not able to create it.
I can place the shapes manually in package geo/ SM or PM, but I think lot of the data does not have it to display in the default setting for our filmsetting.
Please let me know if there is a way to make the shape symbols or not.
Thanks in advance.
Have to ask...why top side venting? Your fabricator will be concerned about contaminants getting trapped and either tent both sides or open both sides.
In reply to Robert Finley:
It was one of the suggested method I saw online. We are trying to find a good way to avoid fill/cap these vias to cut cost. Our assembly side does not like to keep it vias open due to solder wicking.
From what I see, the document shows the soldermask around the via, but not completely covered on top side. They suggest capping the top side is better than bottom side on this article so we wanted to experiment with few different options to see what the assembly will prefer.
In reply to Mstrghettorigg:
What is your via pad to SMD pad spacing? Tenting the via will always be cheaper and more reliable than plugging it.
Or, you can set the soldermask opening to the drill size, or slightly larger, allowing them to flush the barrels.
Thank you for your feedback.
Our spacing depends on the complexity of the design.
I will suggest these methods and see what we would like to go through with.
So I'm assuming that voiding the shape symbol pad is not possible?
I've been working with a similar design problem. You can see that Q3 and Q4 have "multiple drill" via arrays inside their drain pads, and there's a little green halo around each one which demarcates the "void" inside the soldermask shape. This padstack has no soldermask layer attached to it; that layer is defined in the foodprint, instead, and because it's a negative layer... adding "voids" means you've added an area that will have soldermask epoxy in it. Double-negation FTW :p
This allows me a nice seque into a related question: If you look at the above picture, and in particular those 15-via patterns in the drain pads of those FETs; it becomes apparent that there are no voids being created in the GND layer (the tan-colored background), unlike the "real" via which can be seen attached to a trace right above Q3. If these holes are through-plated they will result in shorts between the pad and any/all plane layers they intersect.
If this is compared to U6 (thermally-enhanced TSSOP14), the big difference is that the padstack is defined as a rectangle on every layer, whereas in the FET footprint the padstack is defined as single layer. Now -- I know that the fact that it has vias means that it's by definition not single-layer... but I don't know how to have no padstack (*except* the plated holes w/ clearances) on the layers in which I need no connections. The issue with what's been done to U6 is that the rectangle gets connected to the internal planes with a thermal relief, if I do the multi- rather than single-layer footprints. Kind of defeats the purpose ;)
If you look closely at the yellowish-tan GND layer at U6, there's a funny halo also visible there around the thermal pad. That's a shape that's been drawn, slightly larger than the thermal relief, with it's definition as "full connect". This allowed me to have through-hole parts still getting thermal relief connections, but these thermal pads to have nice beefy copper plane connections.
If the (top copper and top soldermask) Gerber layers are brought into GCPrevue; the result is this:
Which I think achieves the topside tenting thing you were looking for. Sorry -- but I can't find an option in GCPrevue to make the layers semi-transparent. That *might* made the above image a bit nicer to look at... =/
I'd really appreciate some comments/thoughts on this. I hope it might produce more interesting discussion on the tenting, thing, too...
In reply to mpfleger:
Those FETs have a grounding slug that the manufacturer hopes you will SMT reflow solder.
Vias are suggested by the manufacturer if you want to use the pcb to conduct heat or connect the FET center pin to a different layer.
I actually wonder if you can relocate those vias outside of the slug soldering area, if you need to conduct electricity to another layer.
Slug pads with integral vias are usually found in microwave/RF devices to keep parasitic inductance to a minimum. I believe your design is more focused on DC current.
If the goal is to transfer heat... Not sure what benefit can be had from conducting heat to an internal layer directly under the slug with vias. You could add a solder-down heatsink resting on top of the SMT package to dissapate heat away, or maximize the copper area of the layer you are showing us to improve thermal conduction (Thermalloy?)
I know there is aluminum core construction. But, I don't know if the PCB is a reliable solution for removing heat.
I've been playing around with these footprints, and checking the actual gerber output to see if it agrees with what I'm seeing in Allegro. I'm still using 16.5, btw.
The primary issue I'm trying to raise lies with the provision that exists (in Padstack Designer) to put multiple drills into a padstack, even if it's "single layer mode". The problem is that those holes don't actually exist in any other layer except layer one. I get a really entertaining NC drill file for holes connecting layer 1 to layer 1 when I produce the manufacturing files. I'm thinking the "multiple drill" option should probably be grayed-out when in single-layer mode. (?)
If I make these padstacks multi-layer, and put pads on just the top and bottom of the board; there is a bounding rectangle created that attempts to surround them. The kick in the head is that the bounding rectangle isn't getting the x/y offset that's been specified for the multiple drill array, but is just centered within the padstack, and would be sized appropriately if the multiple drill was centered, too =/
(did I miss some critical configuration option that's causing this?)
This should clarify what I'm talking about, and the failure to align the clearance rectangle with the hole array:
I understand what you're saying about using a PCB for removing heat. The reality is that a number of manufacturers (like TI) are using packages that need to use the PCB as a heat-spreader, or as a thermal path to a heatsink proper. I suspect we'll probably be seeing more and more of this kind of stuff as the packages keep shrinking. The TI docs on that part in the "eTSSOP" package are pretty adamant about this being done, and they do put some numbers to the copper thickness and area size on the backside of the board, which suggests they have some faith in the ability of copper to work this way.