Hello, I have a BRD file that contains a large amount of testpoints. I have supplied the test house a board file and they extracted test points of their choosing. Now my fixture might differ from their selected testpoints. Does anyone know of a way to automatically read an ascii testpoint file and compare it to the Allegro testprep fixture one I have. I really need to lock down my fixture to match the test houses fixture for future ECNs. Any help would be appreciated.
"One suggestion is to text edit the Allegro testprep report so it is in the same format as the report supplied by the board house and compare the two files. If your file is too large to edit, you may want to create your own extract file and edit it so the format matches the one supplied by the test house. The extract (extracta) command file (from SourceLink solution 1816263) could look similar to: FULL_GEOMETRY CLASS= MANUFACTURING SUBCLASS = PROBE_BOTTOM NET_NAME NET_NAME_SORT VIA_X VIA_Y PIN_X PIN_Y END To generate output similar to: S!A0!A 00000000!4550.00!4535.00!!! <- via S!E0!E 00000000!!!6350.00!4550.00! <- pin You can download a free eval copy of a nice text editor at: http://www.textpad.com/ that would help you accomplish this. Hope this helps!
Dear ExpertsI have a similar problem to this thread. I am trying to extract a list ofnetname, device pins and x y coordinates and the layer they are on (top or bottom). I'm also looking to do the same with vias - netname, x y and layer (top orbottom if they are blind vias.I originally had this for the extract(a) file. But couldn't find a parameter for 'layer'.
COMPOSITE_PADNET_NAMEREFDESPIN_NUMBERPIN_XPIN_YEND Will the following work?FULL_GEOMETRYCLASS= MANUFACTURING SUBCLASS = PROBE_BOTTOMNET_NAMEREFDESPIN_NUMBERPIN_XPIN_YEND Then I would create a second file for the top:FULL_GEOMETRYCLASS= MANUFACTURING SUBCLASS = PROBE_TOPNET_NAMEREFDESPIN_NUMBERPIN_XPIN_YEND Is probe_top a way to get the components on the top of hte PCB?Then for the vias I was going to do this:FULL_GEOMETRYCLASS= MANUFACTURING SUBCLASS = PROBE_BOTTOMNET_NAMEVIA_XVIA_YENDFULL_GEOMETRYCLASS= MANUFACTURING SUBCLASS = PROBE_TOPNET_NAMEVIA_XVIA_YEND
So I can identify which vias are on which side and which components are on which side.Any insight would be appreciated.Regards,Splash
> Is probe_top a way to get the components> on the top of the PCB?Nope. PROBE_[TOP/BOTTOM] are used for test points most commonly used for bed-of-nails testing. In the footprint, one would use NO_PROBE_TOP to define a shape to keep those test points a certain distance away from the footprint. The shape flips to the _BOTTOM when the footprint is on the secondary side and the PROBE_BOTTOM subclass is defined. I cannot remember if this is done by default.After saving a good copy of the BRD file, check out the menus under 'Route' > 'Testprep'. When test-points are generated in Allegro it puts symbols on these layers to generate a location file for each nail.There are a lot more things to consider but I will stop here since this has nothing to do with what you are currently trying to accomplish.Cheers,Drew
Oh!The pins of the footprint are located at;CLASS: Stack-UpSUBCLASS: pin/topSUBCLASS: pin/bottomThe reference designators are located at;CLASS: Components SUBCLASS: ref_des/silkscreen_topSUBCLASS: ref_des/silkscreen_bottomCheers!Drew