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I am attempting to use phase tolerance to control some relative length rules within a differential pair. The topology is essentially 3 components which I will call A, B and C. The signal goes from a pin on comp A to one on comp B and continues on from B to a pin on comp C.
I would like to set phase tolerance to say 5mils and see the property on pin pairs from A-B and A-C though I could live with B-C being created as well.
The issue that I am having with this is that Allegro configures the pin pairs associated with a given net/diff pair based upon the PINUSE property (and apparently the part CLASS, though I haven't seen this affect anything in my situation.) The pins in question are functionally bi-directional, yet I don't get the pin pairs I would expect if I set the PINUSE property of the associated pins on A, B and C to "BI". Perhaps I'm not thinking about this correctly, but in my mind a bi-directional pin is one that can either drive or receive a signal. As such, I would expect to see 3 pin pairs created when all components are set as mentioned (pinuse = "BI"); A.pin:B.pin; A.pin:C.pin; B.pin:C.pin. Instead, Allegro will only create a pin pair based upon the longest length (A.pin:C.pin).
I decided to research this a bit further and found information essentially saying that there has to be an explicit definition of driver and receiver, otherwise the longest path will be chosen. To further complicate matters I tried the following configuration: A = TRI B = BI C = BI
This yielded the 3 aforementioned pin pairs I would've expected to see on a BI, BI, BI configuration. What is confusing here is that a pin pair is created between components B and C which again, were both set to BI... yet in the previous configuration (BI, BI, BI) Allegro defaulted to the longest path method of pin pair creation.
I can work around this issue by using the following: A = OUT B = IN C = IN. This works fine for my purposes as I will get A.pin:B.pin; A.pin:C.pin as I originally wanted, but it is functionally incorrect in terms of PINUSE which could adversely affect other disciplines interacting with the topology.
To summarize, I would like to know if there is a way to set this up in such a way that I can access the desired pin pairs while maintaining accurate PINUSE properties.
Phase Tolerance property gets applied to the differential pair (i.e. the diff pair object in CM and gets applied to the "whole" net not pin pairs, I think) so I am not sure what you mean by "would like to set phase tolerance to say 5mils and see the property on
pin pairs from A-B and A-C though I could live with B-C being created
If you want to apply length restrictions on pin pairs then group the pin pairs in a match group - this is done in Relative Propagation Delay tab. You can create pin pairs in Relative Propagation Delay worksheet then create a match group by selecting those pin pairs.
In reply to Khurana:
Thanks for the response. I will attempt to elaborate.
You are partially correct in your first statement; phase tolerance IS a property that is applied to the differential pair, but Allegro will break the individual nets of the differential pair into pin pairs according to their PINUSE configuration. Please see the following table:
I did find the following information (which seems all too similar to an IQ Test question) as a solution to a similar issue on sourcelink:
* If there are no RECEIVER pins, then all UNSPECIFIED pins are assumed to be RECEIVERs; otherwise if there are no DRIVER pins, then all UNSPECIFIED pins are assumed to be DRIVERs.* If there are DRIVER pins but no RECEIVER pins, then all BI pins are assumed to be RECEIVERS; otherwise all BIs are assumed to be DRIVERS.
The above seems to indicate that UNSPECIFIED and BI PINUSE types will fill the need of either missing property (driver or receiver.) This gets a bit convoluted when coupled with other pinuse types such as BI, BI, BI gives A:C yet TRI, BI, BI yields A:B, A:C, B:C.
I suppose you can disregard this post for now as I will ask Cadence directly and then post the answer. Thanks again.
In reply to Eric IntAZ:
In reply to annoonan:
Not sure where the problem is, if there's one but Allegro PCB allows you to change the PINUSE in Constraint Manager's Component folder when you choose Properties selector bar.
What's the value of Phase Tolerance for the diff pair? Also, dynamic phase tolerance was introduced recently...can you invoke Show Element on the DRC and post it here?