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Hello, I'm new to Cadence, coming from Altium. I'm using Allegro Design Entry HDL and PCB Editor, rev 16.3.
As part of the new design and "new to designing with Cadence" process, I am creating parts for our library and I'm having some trouble with a TI SON part that includes a thermal pad or power pad. Here is a snap shot from the TPS6120:
At this point, I've made the pads in the padstack editor (but made them rectangles since I didn't know how to make it a rect at one end and rounded at the other) and used the symbol creation wizard to make a SOIC. To make the thermal pad I placed a filled polygon on the Etch/top layer and it is one large pad with the outline like above.
Question: How do turn my filled polygon into a ground pin (or should I not?) and how do I add the soldermask layer to something I've drawn like this?
Question: How do I add vias to my footprint? My plan was to create the via in the padstack editor then place them in the appropriate places but I have some confusion as to whether the pad/via structure is just supposed to sit there dangling or if it should be assigned a pin # (ground).
I did search the forum and came across the thread Thermal Pad Shape with Vias In it a poster mentions that he makes these pads using multiple surface mount style pins. I think I can figure out how to do this but I'd appreciate any tips on setting up the tools and pads so that things are properly done.
Picture of the pad made from pins:
You can draw non standard shaped pads by creating a shape symbol (*.ssm) then add that shape to a pad using Pad Designer. You can add multiple shapes for etch, mask and paste using the same process or use null for the layers in pad designer and draw the mask and paste when creating your symbol. Add the vias to the thermal pad by either going into add connect mode and double clicking to add vias (the same as in PCB mode). You will get DRC's until the symbol is loaded into PCB Editor with a netlist, the vias then take on the.e same net as the pins. The tab pad would be another pin (i.e. pin 21) which would need to be on your schematic symbol connected to GND.
In reply to steve:
steveYou can draw non standard shaped pads by creating a shape symbol (*.ssm) then add that shape to a pad using Pad Designer. You can add multiple shapes for etch, mask and paste using the same process or use null for the layers in pad designer and draw the mask and paste when creating your symbol. Add the vias to the thermal pad by either going into add connect mode and double clicking to add vias (the same as in PCB mode). You will get DRC's until the symbol is loaded into PCB Editor with a netlist, the vias then take on the.e same net as the pins. The tab pad would be another pin (i.e. pin 21) which would need to be on your schematic symbol connected to GND.
Thanks Steve, I will look into the process for creating a shape symbol. I've seen reference to them in my searches but wasn't sure what they were or how you made them.
I wonder if I could copy the shape I already made on the board and paste it into the shape symbol tool?
In reply to erivas:
erivasI wonder if I could copy the shape I already made on the board and paste it into the shape symbol tool?
Yes, but it's not called copy/paste in Allegro. Allegro can export a "subdrawing" (File->export menu). Follow the prompts and think about the origins of the items you want to export (use right mouse to select a body center for example).
Then in the symbol editor use File->Import->Sub Drawing. Again, the origin will need to be thought out.
One thing to be aware of is that the layer names being exported/imported have to be identical. Shapes for pads would most likely be on etch-top and etch-bottom so that won't be an issue for your problem at hand.
Use your color control and find box to filter out junk you don't want to copy.
In reply to redwire:
thanks again, this was helpful. I ended up making the shape from scratch as a flash instead of trying to copy or export it. added it as the 11th pin and everything looks pretty good.
Please guide me how to create Special Symbol (.ssm) file using Cadence allegro 15.2
In reply to Gopintj1:
Not sure if the process is identical in 15.2 (it's such an old version of the software) but take a look at:-
I stepped into the same problem.
What exactly is this:
Add the vias to the thermal pad by either going into add connect mode and double clicking to add vias (the same as in PCB mode).
Where is the add connect mode?
I'm drawing the package as .dra.
When I add pins(+ vias) by Layout->Pins, I get of course the DRC-Errors.
Then, I want to safe it by File -> Create Symbol, but it aborts because of the DRC-Errors.
In reply to Bummibaer:
The Connect mode is under Layout - Connections, you can double click to add vias as thermal pins. The via type is defined under Setup - Constraints - Physical - Physica; Constraint Set All Layers, look at the default rule and set the via to the pad you want to use. Remember when you add the vias you will see DRC's but this is normal. There is no netname in the symbol. When you load the symbol into a board using a netlist the vias will take on the netname of the pin that they are attached to.
In v16.6, "add connect" means to do one of 3 things: 1) punch the "add connect" button in the route toolbar located GUI left by default; 2) hit (F3); OR 3) choose Route/Connect. I do not view add connect as a MODE. Modes appear under Setup/Constraints or define an APP Environment. Rather, it is one of the most commonly used commands, so common in fact, that I have it programmed into one of my mouse buttons. When you are in Generaledit/AppMode (the default environment), and you hit the add connect button; you are laying down etch or traces until you double click. Whenever you double-click, you get a via--as in when you want to change layers.
In reply to TommyBrunet:
I am using version 16.3 and when I go to add connect mode" there is no option to add via.
Also if I use Add PIN and place Via it gets PIN assigned to its class and not Via.
only way I can see of doing this adding via to thermal pad is qithin board file later as it is not possible using Drawing.
In reply to nigelf:
1) In 16.3, the via status field appears in the options window, third field (drop-down menu) from the top.
2) Before vias get populated to that field, in a particular ".dra" file, vias must exist in the CAD part library, and then be setup in the constraint manager\ Physical Constraints\ double-left-click the default via cell (see image).
3) The "Edit Via List" window appears. Double-left-click vias in the library field to add them to the Via list field (see image).
4) Hit OK and X out of the Constraint Manager.
5) Now when you choose the "Add Connect" comand and begin to lay down etch, the via appears in the options window, via, pulldown menu (see image).
Thanks so much for detailed description.
Following your direction my QFN package is complete.
I've got a similar task that I'm stuck on. I've been asked to create a 50 mil bare copper edge trace all the way around the outside edge of a PCB board design.
I made a 50mil x 4000mil smd pad and a 50mil x 3500 smd pad in pad designer and a 200 mil x 200 mil pad for the corners. Then I opened Orcad and created a new mechanical symbol and imported the smd pads I made and laid them out so that they made contact in the 4 corners and is the correct size. I then laid the 200 mil corner traces in the 4 corners. The result was lots of DRC errors but the size and layout is correct.
Is this the correct way to make this layout?