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Please help me ("for dummies") with a problem!
When I run PSpice, I see in *.out file(Allegro Design Entry 16.3):
ERROR -- Node in is floatingERROR -- Node supply_0 is floatingERROR -- Node unnamed_1_bft92/plp_i1_e is floatingERROR -- Node diod is floatingERROR -- Node unnamed_1_bfr92a/plp_i2_b is floatingERROR -- Node unnamed_1_bfr92a/plp_i2_e is floatingERROR -- Node unnamed_1_r_i5_2 is floatingERROR -- Node X_X1.6 is floatingERROR -- Node X_X1.5 is floatingERROR -- Node X_X1.7 is floatingERROR -- Node X_X1.4 is floatingERROR -- Node X_X1.8 is floatingERROR -- Node X_X2.6 is floatingERROR -- Node X_X2.5 is floatingERROR -- Node X_X2.7 is floatingERROR -- Node X_X2.4 is floatingERROR -- Node X_X2.8 is floating
Why is that?
You will also have a message in the session log that your design is missing a "0" node or symbol. PSpice requires that the design has a reference node called "0", you can call a net 0 or connect a 0 symbol from Place>Ground, pick the "0" symbol from the Capsym library, connect this to the reference net.
In reply to oldmouldy:
if the error message still persist connect a high value (1 giga) grounded resistor to the node that the message indicates
In reply to tltoth:
Thanks for the advices!
I mixed up the "0" and "supply_0 "((((((
What does the "supply_0"?
In reply to Tony Stark:
It is a net name. Attach a picture of your schematic please. It will be easier to help you.
During DC Bias analysis each capacitor is assumed to be open circuit [xc=1/(wC), if w=0 xc->OO] and each inductor is short circuit.
So there is no DC path between T2 emitter and R1 because of C2.
Put an 1g resistor parallel to C1 and C2.