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Hmm...the back annotation should work. What was the *exact* technique that you used? Was the schematic and board synchronized before the backannotation occurred? What were the error messages specifically?
In reply to redwire:
As far as I know, the two files are not synchronized. No idea how to do that. We used to outsource our boards and now we are doing everything internally. I have all the files, but they're a big mess at the moment.
For the back annotation, in Layout I just did Back Annotate from the Auto menu. Then in Capture, I open the DSN file, click on schematic - page 1, then select Back Annotate from the Tools menu. That window pops up and I select the Layout tab, process entire design, update instances, and finally select the appropriate SWP file. I tried it this morning and it looked like it processed OK, there were no errors, but my schematic didn't change.
In reply to nicknails:
Sound like the netlist was manually modified in allegro (edit logic): no other way to change footprint.
When you attempt to modify logic in allegro, you get a warning and you have to set a variable in order to go ahead: no way to modify logic without be aware of that.
In logic have be modified, there is no way to backannotate in schematic: the link is broken.
If logic has not been modified, the footprint can not be changed.
In reply to jch teyssier:
That could definitely be a problem then. One of the parts was changed along with some nets. Is that a definite no-no? What are things that can be changed and back annotated to the schematic? Obviously designators, but what about footprints, values, etc.?
How would I go about fixing this? Do I adjust the schematic and then annotate to the board?
nicknailsHow would I go about fixing this? Do I adjust the schematic and then annotate to the board?
Yes! Allegro is a netlist driven layout tool. Other tools like PADS can be driven as a layout driven tool.
So in Allegro when a new footprint that is not an optional footprint is needed, the netlist needs to be brought in with the new / alternate footprint. Can you resynch? Well yes but it means having to make the changes that match the board over in the schematic and then package it back to the board. If the ECO report is clean then it'll backannotate later on.
OrCAD/Concept/Allegro is not very forgiving when this is not followed.