Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm having a similar problem when attempting to export ODB++ from .brd file. It seems to break at some point and starts spitting out the error messages referring to D:\vSureSRC\ like the OP. The last few lines of the log_brd2odb_x.txt are included below. The fifth line is where this log diverges from other successful gererations of ODB++ files for our other boards.
Done - 0 seconds
Create step profile ...
Complete step ...
write file - G:/XXxxxxx/XXXxxxx/hw/XXXXxxxxx/hw/rXvX/allegro/odbjob/steps/pcb/eda/data.Z
*********** ERROR INTERNAL 26Feb2013.093354.892 4676 9.1(1) Windows Vista
(hIn != ((HANDLE)(LONG_PTR)-1)) at D:\vSureSRC\s91\gen\gen_fs.c 1930
*********** ERROR INTERNAL 26Feb2013.093355.766 4676 9.1(1) Windows Vista
System open call error : No such file or directory at D:\vSureSRC\s91\gen\gen_fs.c 1930
file/dir causing error : C:/MentorGraphics/Allegro Export ODB++/tmp/brd_2/comps-genesis186ad.XXxxxx-Xxxx.4676
*********** ERROR 26Feb2013.093355.766 4676 9.1(1) Windows Vista
Object id = 1151, type = 3
*********** ERROR 26Feb2013.093409.846 4676 9.1(1) Windows Vista
colors file does not exist - C:/MentorGraphics/Allegro Export ODB++/.genesis/colors
*********** COMMAND 26Feb2013.093409.906 4676 9.1(1) Windows Vista
Something happened to my board file when my computer crashed due to a graphics card failure. After DB doctoring after the crash everything appeared to work fine; constraint manager was fine, all components imported worked fine, and gerber generation went off without a problem. However, now that I try to export an ODB++ file(s) the symbols folder within the ODB++ archive is empty and this is something our contract manufacturer needs. I tried the suggestion of changing the artwork to RS274X and decimal places but to no avail ( we use this format so I actually moved it away and back to the RS274X settings)
Did anyone ever get resolution on this? Right now I'm attempting to place-replicate an entire board design from the newer failing brd file to an older file that still generates ODB++ correctly but it's not fast or perfect and we've already lost some time due to this.
Thanks for any help