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I encoutered a problem while netlisting and updating pcb desing.
I have a 16.6 capture desing with its pcb. Now I need to update few things in it, so I copied the desing to another folder, add few wires and netlist the desing, so far this is ok. After succesfull netlisting I updated the pcb, where input it the former pcb, and named it with new name (though the error is thrown with the same name too)
The error is displayed in the image link.
(---------------------------------------------------------------------)( )( Allegro Netrev Import Logic )( )( Drawing : SK28LI11.brd )( Software Version : 16.6S005 )( Date/Time : Fri Mar 22 12:00:40 2013 )( )(---------------------------------------------------------------------)------ Directives ------RIPUP_ETCH FALSE;RIPUP_DELETE_FIRST_SEGMENT FALSE;RIPUP_RETAIN_BONDWIRE FALSE;RIPUP_SYMBOLS ALWAYS;Missing symbol has error FALSE;SCHEMATIC_DIRECTORY 'G:\ANALYZY\SKOP28T.1593\SKOP28LA\HW\SK28LI10\allegro';BOARD_DIRECTORY '';OLD_BOARD_NAME 'G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/SK28LI11.brd';NEW_BOARD_NAME 'SK28LI12.brd';CmdLine: netrev.exe -y 1 -z -i G:\ANALYZY\SKOP28T.1593\SKOP28LA\HW\SK28LI10\allegro G:\ANALYZY\SKOP28T.1593\SKOP28LA\HW\SK28LI10\allegro\SK28LI11.brd G:\ANALYZY\SKOP28T.1593\SKOP28LA\HW\SK28LI10\allegro\SK28LI12.brd------ Preparing to read pst files ------Starting to read G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstchip.dat Finished reading G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstchip.dat (00:00:00.09)Starting to read G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstxprt.dat Finished reading G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstxprt.dat (00:00:00.01)Starting to read G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstxnet.dat Finished reading G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstxnet.dat (00:00:00.01)------ Oversights/Warnings/Errors ------#1 Run stopped because errors were detectednetrev run on Mar 22 12:00:40 2013 DESIGN NAME : 'SK28LI10' PACKAGING ON Sep 10 2012 04:46:09 COMPILE 'logic' CHECK_PIN_NAMES OFF CROSS_REFERENCE OFF FEEDBACK OFF INCREMENTAL OFF INTERFACE_TYPE PHYSICAL MAX_ERRORS 500 MERGE_MINIMUM 5 NET_NAME_CHARS '#%&()*+-./:=>?@[^_`|' NET_NAME_LENGTH 24 OVERSIGHTS ON REPLACE_CHECK OFF SINGLE_NODE_NETS ON SPLIT_MINIMUM 0 SUPPRESS 20 WARNINGS ON 1 errors detected No oversight detected No warning detectedcpu time 1:05:06elapsed time 0:00:39
--------------------------------------------------------------- end of netrev
Neither of this error outputs are very descriptive. No SAV is saved as mentioned in the error message, also dbdoctor on the pcb desing have not helped.
Would you please advice me how to solve this? We have no problem with this pcb updating so far. Could it be somehow connected with our recent update to 16.6. hotfix number 5 ?
The path contains a . which Allegro might not like. Try removing this from the directory name and see if that helps.
In reply to steve:
In reply to Justus:
If possible downrev to 16.5 and see if the problem persist.
I would suggest submitting this to Cadence.
EMA Design Automation
In reply to BillZ:
Downgrade is hardly possible. Well, where can I submit to Cadence please?
I figured out, that when I do a smallest change like changing connector in the schema, this error with generating emerges.
Depends on where you bought the software. If you purchased it from Cadence direct then you will have a login account at www.support.cadence.com. You can file a Case for investigation. If you bought from a Cadence channel partner then contact the relevant one http://www.cadence.com/Alliances/channel_partner/pages/default.aspx.