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Topology extraction - probe. Simulation fails vias due to via model errors.
Tried the board simulation in 16.3, 16.5, 16.6 errors in all attempts. Rexacted the via models from the board file, failure.
Moved to a different box to run the simulations, there were no errors.
Differences between systems - Windows 7 vs. Windows XP. Simulations run on windows XP box.
Question: Is there a known issue or work arround for PCB SI with windows 7?
Note: Latest hotfix (10/23/2013) on all versions.
are you able to extract the topology for the address bus of DDR?
In reply to Sumit Sharma:
The board that I am simulating is a telepony based platform that we designed it has no DDR, but sevral IBIS models with PCM SPI and I2C interfaces.
In reply to Wild:
Resolved the topology extraction isssue.
Turned down the UAC in windows 7.
This also resolved the issue I was having with imbedding OLE objects into Capture.
Update fromcustomer support:
Deleted the temp and tmp paths in the user variables.
Lowering the UAC only solved the OLE immbedding in Capture (ORCAD)