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am having problem in design reuse with allegro. i am using hierarchical
design in which two external designs are instantiated twice.(total
modules = 4(M1,M2,M3,M4)) but after all steps given in capture tutorial
and final netlist generation when allegro window opens, it has all the
four modules but in M2 half of the some clines has the net_name
of M1 and the same is repeated with M3 and
M4. please advise what is going wrong? i am using ver 16.0
Has anyone used the feature of design reuse by making .mdd file in
allegro through orcad capture version 16.0? please let me know the stepwise process. i have been stuck up in my work due to this problem.