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In my develop board there has a DIMM connecter,i will simulate the board with the Dimm board,but i have the DIMM board ebd file,i have translated the ebd file into boardmodle file? how can i use the boardmodle? i can not assign the boardmodle to the DIMM connecter? can you tell me the next step? thanks !
You need to use Designlink to link with your boardmodel. To do so, in PCB SI, click Analyze->SI/EMI Sim->Initialize... Singal Analysis Initialization dialog will be shown. Click New DesignLink Button to set up. Hope this helps, Lance
lwang: Thanks you help! The step you tell me i have tried,i have created the designlink ,but i can not get the topology by using Cmgr.and there is a messsage displaying. the follow is the message "" WARNINGS: WARNING: You are extracting from a BoardModel and will not get the correct interconnect data in SigXp. The Allegro PCB SI product does not fully support BoardModel extraction in this release. While the buffer models are correct, the BoardModel interconnect is not. Be sure to delete the interconnect and redraw it to reflect the interconnect contained in your BoardModel "" can you help me ? thanks by the way ,canyou tell me your email?
This is known problem. The reason is that the topology shown in SigXp doesn't contain the correct interconnects in the boardmodel. However, if you simulate them in the SQ(PCB SI, not SigXp), the result is correct. The issue only exists in the SigXp. My email is email@example.com. Be free to send the questions to me directly. Lance
lwang: i find when i use .dml file which directly come from manufacturer,i can get the topology. but the file which i translated from .ebd file can not get? can you tell me the reason? And not all topology can not get.for example, i can get the ddr address signals topology,but the data signals can not
I would believe that EBD should be translated to DML before link to Designlink. It means after EBD translated to DML then both DML boradmodels should be the same. So, you should be able to extract them to SigXp on both cases. But as I mentioned before, I don't think the interconnects in the boradmodel partion are correct. Please check them againest to BoradModel file (DML or EBD). Hope this helps. Lance
LanceI have EXACTLY the same problem as the previous poster, except that I can't get a DML from the vendor, I only have a.ebd, which I've converted to DML in using MI, so I have no choice but to try and use it. I know the interconnect is wrong, however I/O buffer models are not extracted at all, so all the inputs to the DIMM are OK, but not the DQ's. Any idea why ?Also, could you please explain what you meant by "simulate in SQ (PCB SI not SigXP) - are these not the same thing ? I have PCB SI 230Thanks
The attached application note may be of assistance in converting an EBD and including the buffer models,
Thanks a lot - that's the first time I've come across the perl script mentioned, which should allow me to get around the interconnect parasitics limitation, however I don't think it explains why the I/O buffers models are completely missing - the procedure for creating the Board Model is exactly what I used but when I extract a net containing a DQ on the DIMM, the net just terminates in an end-point, with the correct pin number, but no buffer model. I can manually add the correct buffer model so the model is not missing - I guess I'll just have to do this if I can't get the extraction to workThanks again for your help
OK - I/O buffer extraction problem is fixed I think (thanks to Abhay Apte at Cadence) - problem was with PINUSE not being properly extracted from .ebd file - also took me a while to persuade PCB SI to let go of all the temporary copies of the bad Board Model which it had hidden away and kept trying to useCan anyone explain the difference between simulating directly from PCB SI and from SigXP ? Is it the same simulator ? Should the results be EXACTLY the same for the same inputs ?
Aball,which version of PCB SI are you using? PINUSE issue should be gone for long time. (that was one.) If you still have the issues within 15.5.1 or later version, you might need to contact support for a bug report.The reason for different simulation in SQ and extracted to sigxp is that extraction didn't extract correctly for the interconnect in boardmdoel. if you simulation in SQ, everything is fine. Read the appnote that djs mentioned should help you for a workaround.Hope this helps.
Part of the problem/difficulty is getting the tool to write and "see" the *.brd file it writes to represent the EBD. After you load the BoardModel into the DesignLink editor you should "OK" to close the form. In the command window you'll note that the tool writes a .brd into your project directory. Once that's done, then re-renter the DesignLink editor and you'll find the rest works much better.Donald