Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm looking for information (links, documents, advices, etc.) on how to run a SigXplorer design in batch mode.While it's easy to find in the tool's course book the tlsim batch mode documentation (Appendix A), I'm still missing a full flow - for example how to obtain from the SigXplorer design (.top file) the spice files (main/stimulus/comps/interconn.spc) and other required inputs for the tlsim run.Thanks,Marcelo.
Hi Marcelo,I've spent a lot of time working with the SPICE files underneath the GUI. It is powerful, once you get the hang of it. Some ideas for you:1) Type "tlsim" at a command prompt for a dump of the usage options2) There is a switch to run SigXp on a .top without running up the GUI, I think it is -nograph.3) All the .spc files are produced, and then called from main.spc. You only have to tell tlsim where to find main.spc.4) There was a nice appnote on allegrosi.com written by Patrick Riffault on how to batch SigXp .top files, but I can't seem to find it at the new site. Anyone know where it went?Hope that helps,Donald
Hi Donald,Thanks for your reply.I successfully "played" a bit yesterday with tlsim.What I'm missing is something like you mentioned in item #4, a flow to get all the required inputs for tlsim from my design (from .top file to .spc files and any other required input).I believe it should be part of what happens when selecting "Analyze>Simulate" in SigXplorer (Skill function run?), but I need to find some documentation about it...Regards,Marcelo.
The revised application note can be found at: http://www.cdnusers.org/Articles/Download/tabid/163/Default.aspx?title=SigXplorer%20Batch%20Mode%20Simulations
I ran a .top simulation case that generated the *.spc in sigxp.run\case0\sim1For example, I obtained an interconnect.spc as follow:.subckt DESIGN_icn_ckt 1 2 * Display all elements first NTLidlPart_21 (1 0) (2 0) +L=0.0254 rlgc_name=STL_1S_1R_5 file=./ntl_rlgc.inc
.ends DESIGN_icn_cktLater, I went to the command prompte, and input:spc2spc interconn.spcI obtained the following spice file, main_gen.spc:.subckt DESIGN_icn_ckt 1 2
XTLidlPart_21 1 2 0 rlgc_sub1
.subckt rlgc_sub1 1 2 9999X1_1a 1 100 9999 rlgc_sub1aX2_1a 100 101 9999 rlgc_sub1aX3_1a 101 2 9999 rlgc_sub1a
.subckt rlgc_sub1a 11 12 999C1_1a 12 999 5.3456e-013L1_1a 11 13 4.40665e-009R1_1a 13 12 0.0611742
.endHope this is helpful.
Elie,Looks like you meant to post that reply to the other thread about cutoff frequency?What you are showing is how spc2spc converts the proprietary NTL (lossy, frequency-dependent transmission line model) into small RLC lumps that any spice tool can read. It will choose the number of lumps based on the length of the line, and will use the RLGC data in ntl_rlgc.inc to determine the best RLC values.Donald
Actually; he was wondering, and I quote:"I'm still missing a full flow - for example HOW TO OBTAIN from the SigXplorer design (.top file) the spice files (main/stimulus/comps/interconn.SPC)"So he can't find the spc files, so I indicated the directory of the spc files could find. I also indicated how to get the spice files; Although I was not sure he needs it. Yet, I am certain this would be of use to many in the industry.I have not gone detailing the batch mode because I did not 'play' with it recently.The other question is simple, you only need to think which section of the signal contains the changing fields.This is it. Although, your manuals don't mention the equation, and I am not defending you,yet it is well known relationship.
" Although, your manuals don't mention the equation"At least the manuals that I have seen..
"..which section of the signal contains the changing fields.."The signal is composed of fundamental and harmonics of high frequenciesYet, It is the edges that indicate the presence of several high frequency components, which trigger varying field effects, and increasing electromoagnetic force that willimpact the line elements
And let's emphasis, that beside the edges, the middle sections are statics