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Hey allIn my design i am having processor to L3_cache interface in that for Echoclock signal going from L3_cache to processor when i did SI i am getting Monotancity FAILs, i tryed to vary the length and resistor value even also i am not getting the result as PASS. my processor is at 2.5V and L3_Cache is at 1.5 v mode i selected proper model for Simulation.I am attaching the topology file any one can suggest me what i have to do next.
It's odd you would see this behavior with only one load. Note that monotonicity is not a concern for a synchronous signal, but it seems you're saying this is a clock. I would move the resister closer to the driver (to the TOP layer) and possibly remove it. Since you have a 1.5V part driving a 2.5V part, it's possible you're not even reaching the Vih required by the 2.5V part (and hence the FAIL). In that case, you'd have to either add a pullup resistor (assuming the L3 output could handle it) or find a more suitable L3 part.Hope that helps,Donald