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In my board, there is a DIMM and 2 DDR chip. Now, i am executing front simulation. I use the designlink to link my board and DIMM. But i found the wave is always incorrect. If I romove the DIMM model from SigX, it is ok. And my workmate told me the interconnection is incorrect from the DML model of DIMM. How to construct a model in the SigX from DML file. Thanks first.
did you simulate the signals on the memory-chip-pins on the dimm module, or you simulated on the connector pins? it doesnt matter what you simulate on the dimm-module-pins. sometimes it looks bad at the module-pins, but it doesnt matter. simulate chip-to-chip.the dimm connector must not have IO models assigned, just an empty ibis device model. the dimm should have a board model (imported .ebd with its chip .ibs files) and connected with designlink to the motherboard. for me, it worked.check this:http://www.edaboard.com/viewtopic.php?t=254948&highlight=ddr(this was simulated in hyperlynx on an older design)
Thank buenos for your answer. I have solve the problem already one month ago. The question is that the topology extracted from the .ebd file will be incorrect. And when i extract the topology, the SigX will pop up a box to inform me this. I have compared the topology between the extracted topology and the topology descripted in the .ebd file, the difference is that the length of the signal line. the extracted length is much longer than the exact length.but when i do the post-simulation, the result is correct becaust i do the simulation under PCB SI not SigX. So just do not extract the topology from the ebd file when you do the post-simulation. when you do the pre-simulaiton, please modify the length of signal line according to the .ebd file.