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I would like to learn about test preparation (testprep) beyond what the User Guide has to offer in the Preparing Manufacturing Data for Allegro 15.5
This question could be answered in a couple different ways. 1. On the Design side, You need to setup the database correctly to ensure you have test sites which are not covered by solder mask, on the correct centers, clear of / not under components and large enough to be tested. Most of these can be easily setup inside the Allegro editor to yield a testable product. 2. On the Assembly side, You will need requirements from either the ICT Engineer at the PCB Assembly house or the ICT Fixture manufacture or both to work out the test strategies for your product. There is a lot of things to consider which you really need to talk with the Assembly / ICT Folks your company works with to get product shipped. NOTE: This should be the first thing you do before you begin a design that requires testing seeing that some of the changes may need to be driven at the circuit/schematic level.
In addition to what Mike mentioned, it is advantageous to ensure that your via and/or thru-pin padstack surface pads are large enough to accommodate test probes and that they are not solder-mask encroached when they will be used for test. In my experience a 35 mil minimum diameter surface pad is usually desired but 30mils may be acceptable for some test vendors. The minimum testpad spacing, center to center, is usually 50mils but should not be the nominal. 100mil spacing is much more desirable. Test pad density must also be considered. The goal is to provide test probe access for 100% of the nets, but this may not always be possible. Another way to help ensure that all nets are testable is to fanout all pins of SMD/BGA devices. This is not a guarantee that they will be testable, but will certainly help. The bottom line is that you will still need to consult with your test fixture vendor for specific DFT requirements. Randy
I figured I would add a little more on the topic. Everything Randy as stated is valid and I agree with it 100%. I just wanted to share some of my experiences as well. Out of the gate I pretty much fanout everything with test vias or setup my design rules to space vias away from pins and other vias to meet my ICT spacing requirements. This gets you very close to 100% tested as long as you have the space to fanout vias such that they are on a viable test site. Of course any nets that are fully routed on the surface I used a surface test via instead of a thru via. Depending on the density of the design you may not be able to archive 100% testability due to space or electrical rules concerns so your fall back is explore with the ICT Engineer the possibility of using Boundary Scan or JTAG testing to archive 100% testability. Not to stress the point again but as Randy stated you really need to consult with your test fixture vendor for specific DFT requirements. Mike