Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I have a 2.2 amp signal that needs to enter a backplane connector, but due to pin spacing and pad dimensions, I am unable to route a 60 mil trace.(pins are at 100 mil spacing with 40 mil pads, which leaves max trace thickness of 20 mil in between pins)Should I neck the trace down, or should I break the trace down to two samller traces entering the pad.Any help would be appreciated.
I'm not a layout person but if someone has decided that you need a 60mil wide trace, do not neck down.Split the trace up into several paths whose width total is as close to 60 mils as you can get. Why not use 4 20mil wide traces in the pin field that meet at the pin(s)?
I would suggest using a cooper shape to flood thru the connector pin field to make the connection. It is much easier than dealing with multiple traces. These shapes should be on the surface of the PCB so they carry the most current. One thing to note, if the backplane connector is not Press Fit then you will need a thermal relief on the pins that connect to the cooper shape.Hope this helps,Mike CatramboneUTStarcom, Inc.
I appreciate the replies, Great suggestions.Mike, one of the problems with running a copper pour is that I have multiple 2.2 a signals on adjacent pin pairs. Plus I have to run them as diff pairs. Its a signal and its return path. So it looks like multiple traces it is. Should these be run on different layers ? Same Layer? Can I run one single 60 mil trace and then break it down to three individual 30 mil traces only where I need to?Thanks for all your time and helping me learn.