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Hi guysHas any you used the Allow pin escape insertion feature on the Automatic TestPrep ?i understand that this feature adds via (as ICT ) so it needs to check/move all traces in all layers where it wants to add a via.I have a board of about 3300 nets and want to add ICT's to (only 2700 need ICT).when running the the TestPrep with the Allow pin escape insertion feature checked then the ICT insertion rate is very slowand when i say slow i mean 63 nets proccessed in 11 hours (over night)i have a strong PC with XP Prof with 1G of Ram and Allegro Preformancewhen i run the same just without this feature then it finishes after about 1 hour ( with 3 passes - eg. 3 probe types enabled) (results are 1300 ICT added out of 2700 nets need ICT)Has any of you used this feature ? with any success ?am i doing something wrong ? or did i forget to do something ?attached the testprep automatic form and general parameters TAB with checked featuresthank you for the helproby
Roby, I have not seen this in the past but it has been a while since I asked TestPrep to add in a large amount of missing test points using the "auto insertion" feature.I have a couple tips for you that may help you figure out what is going on.1. Test Prep does not allows add test points if it creates a DRC. It something does not do a good job bubbling traces away from a newly added test point which can cause addition failures because it creating DRCs. I would recommend you check "Disable cline bubbling" in the Testprep Parameters form and see if you can get more test points in using via replacement. In most cases you can easily clean up the DRC that are left behind after the test point is added.2. Dynamic shapes appears to prevent the addition of test points using the "auto insertion" feature so I would remove them prior to running the auto insertion pass and see if you get a higher completion rate. Of course generate a Sub-Drawing of them to be added back in later.3. Hilite the nets that are missing test points and see if you could find a test point location that appears to be a good test site. Try to add a test point manually to an existing via and if it fails review the error echoed on the command line to investigate it further.Overall, during the fanout of the design I attempt to space the vias out is such a way so they can be used as test points so I never run into the situation that you have that no test point sites are available.Hope this helps,Mike CatramboneUTStarcom, Inc.
thank you for the info
but my main question was about the rate of automatic testprep worksi now deleted all shapes in the design an rerun itaftre 4 hours of work it processed 12 nets out of 3263 ( see picture attached ) and it is still running ......i also run it with out the allow pin escape and it runs fast enough ( about 1.5 hours with 3 diff probes)another question i have about the manual ICT it only adds ICT (SMT) on via or trace or padbut if i want to add near an existing via / pad/trace ( and then connect to it ) it is not possibleso i put it on a pad with DRC and move it and after that route to it ( very complicated !)is there a better way to add ICT on adense board ?same problem when i want to add ict over a trace in the middle of the nethow can i do it ?i first added avia manualy then tried to replace it to ICT with no successo i added a small trace out of this via ( on bottom ) and i was able to add on the line/trace a smt ICT - when tried to move the SMT ICT over the VIA got a DRC again is there a better way to insert a TH via ICT on a trace running on internal layer ?thank youroby DrathMEMTEK Elec Eng
Roby,I sort of didn't answer your initial question. It is hard to tell what exactly is going on.. It is running the old allegro no-via router router to insert the additional test sites.Sometimes the old router would run very very slow when you had your routing grid set too fine so I did a little test board and found out that this is still the case.My Test board ran for 10 minutes and was made up of the following:- 1 inch sq PCB- 10 nets- 6 components- Routing grid set to 1 milWhat is your Routing Grid set to ? This sounds like the reason why it is running so long.Your question: "Manual ICT only adds ICT (SMT) on via or trace or pad but is it possible to add it near an existing via/ pad/trace" I believe what you are looking for is to stub off of a existing via/pad/trace. What I have done in the past is setup my TestPrep Parameters and develop a small script to stub off a feature then add a test point which I alias to a function key. Here is a small example:# Add test point stub script# Enter add connect command and select trace # to be tested prior to running this scriptsetwindow pcbipick 0 -100 next testprep manual ipick 0 0done add connect# End of Add test point stub scriptOf course you will need to tweak the script a little to work for you. Your question: " first added a via manually then tried to replace it to ICT with no success"You need to define a Thru Via under the Padstack Selection tab and also check the Replace Vias box at the bottom for it to work correctly.Your question: "I want to add ict over a trace in the middle of the net" "better way to insert a TH via ICT on a trace running on internal layer"As long as you define a SMT TestPad Padstack under the Padstack Selection tab you should be able to add a test point in the middle of a trace. Note: This only works for traces on the external layers because it uses a surface pad not a Thru hole test point.Hope this helps,Mike CatramboneUTStarcom, Inc.
Hi Mikethank you for the effort and the share of your idea'snow i understand that a "OLD" router is involved i understandi see that there is a log being generated tprouter.log ( which i don't understand at all)but i found that it includs a time column which was in average 4-5 minutes i assume per try/viaany way my board is about 110 Sq in and the grid was 5 mils.i changed it to 50 mils and rerun itnow in ran about 5 min BUT... only 3 ICT inserted !! (2-3 seconds per try in the tprouter.log)tried with grid of 25 mils and it ran 14 minutes with 5 ICT !?!(7-10 seconds per try in the tprouter.log)another try with 10 mil grid (which is still running) i get about 1 minute per row in the log fileit seems that when the allow insertion is enabled that the regular via replacement or smt over trace (on bottom) is disabled - it is not logical !when i ran it with 5 mil grid with out the allow pin insertion checked so only pad stack replacement and smt ICT added on tarces was done there were 1300 ICT inserted in less then 30 minutes ( in a faster machine )when i understood that grid may cause the algorithm not to find possible ICT locations that also satisfy the grid i decided to lower it to 0.1 mil and run it without the allow pin insertion and see if i get a higher ICT count ( more then 1300)the result was the same i think i got the exact ICT countso my theory is not right !any way i understand that the preofrmance of the automatic pin insertion feature is less then POOR ! or else you can suggest any thing else?it is not working as expected.about the idea of script ( and alias) it is very goodbut it lacks in that the length and direction of the stub are different for each and every case.so i my idea is : (did not try it yet)after adding the stub as desired ( direction and length)to excute ( by funckey x "done;setwindow pcb;testprep manual;ipick 0 0;done;add connect"done ( of the previous add connect)setwindow pcbtestprep manual ipick 0 0done add connectand then continue add stub to the next placedo you thing it will work ?about the replace regular via to ICT one i probably did something wrong.since i have it defined in the replacment table TAB and it is enabledabout my last questioni meant that i want to add an ICT in amiddle of a trace that runs in internal layer!so i want to be able ( theoretically ) to add a TH ICT VIA on the middle of an internal trace.and to benefit from the good push and shove feature of the allegro.so now after your tip about the script i guess i can change to fit this case alsoor else you have a better solution ?again thank you very much for your effort.Roby DrathMEMTEK Elec Eng
Hi Mikeone more thing i just foundi decreased my max via displacement from 300 mil to 50 miland tha process is faster but still relative slow to the try without the allow insertionmax 300 mil displacement with 5 mil grid gives 3600 possible via sites to be checkedwhile max 50 mil displacement with 10 mil grid gives 25 valid ICT sites to be checked !it still does not explain why when i ran it with 50 mil grid ( and other 2 feature checked beside allow insertion)it only added 3 ICT's ?from one point of view you want small grid so more via's can be replacedform the other hand you want higher grid to reduce run timewhat is the optimum ?or maybe it should be run in 2 stagessmall grid without insertionand then ( in incremental mode ) higher grid with allow insertionwhat do you think ?so now i run it (with 2 stages ) and see after few hours what is the progressRoby DrathMEMTEK Elec Eng