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Hi Everybody,I am facing some problem with the copper pour in the outer layers. I have done Fan out for SMT components (small trace with via). The GND via will be connected to the inner layer plane.When i flood the GND copper in the outer layer, i am getting somany "line to via" spacing DRC errors. I could able to clear these erros by touching the trace.But if i want to modify the outer layer copper shape at any small corner, the same number of DRC errors are repeating.I have attached PDF snap shot of the same error.I request your expertise and need solution.Thanks in advance.Sriram
Switch OFF the same net DRC.Regards,Kishore
you can try picking up the copper (move) and put it down without moving it (ix 0). and / or run dbdoctor.also, i wouldn't worry too much about these drc's until your about done with the board.
If there are too many copper shapes on the layer, then pickingup each shape and incrementing with "0" would be cumbersome. I would rather suggest you to turn the Same net DRC "OFF".Regards,Kishore
I made same net DRC in OFF condition. But still i found few errors. I tried with the move copper by ix 0, but no use.Some how i removed all DRCs, i have moved one via. Strange! i got so many errors.
Go to the Global Dynamic Shape Parameters, and on the Clearances tab set the Oversize value to 0.2. This will eliminate those errors.Regards,Harold
Anytime you have a Cline routed inside of a shape it will break up into individual Cline segments at every vertex. What is actually occuring in your example is the Cline is not exactly going straight into the Via and there is a Cline jog undernearth or very near the edge of the via pad which clearance is being checked to because the Cline is being broken into individual segments.Turning off Same Net DRC is a good option to eliminate the DRCs but you may eliminate DRCs that you would want to see.