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I have a BGA with a uVia on its pad, and have set under Setup -> Constraints -> Set Values.. "Pad/pad direct connect" to "All Allowed" but a DRC error on pad saying " Top, minimum Blind/Buried Via Stagger distance " appears (see attached image). Does anybody know how to configure the tool to avoid this, without changing the "Min BBvia stagger" option to null?
I guess the PCB editor thinks that the uVia on pad is a short, and then flags that DRC error.
Thank's in advance,
Do you have a spacing or constriant area rule set to this net?If you do, make sure your tables are set correctly.Good Luck,Oscar Miguelino
Set min "BB via gap" under spacing rule and don't define the same for "Min BBvia Stagger" under physical rule but you can set "Max BBvia Stagger" rule.Regards,Satya
Ok, so as I understand, I have to set "BB via gap" to whatever value I want (depending on the routing class) and "Min BBvia Stagger" to "0" to avoid the DRC's of via on pad's, do I?Thanks,Luis.