Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
My quesiton is the following, and is looking for any comments and experience. I am converting from Orcad( Design Entry CIS) to Concept( Design Entry HDL) for schematics entry. From Orcad, I am able to renumber the whole schematic, or set all reference designator to ?, so that I can update the entir design. Now, in DE HDL, I see that reference designator started to be ?, and after I "export physical", I can then see the updated refdes like R1, R2..etc. How do I setup so that I can see all the reference designator converted to ? such as R?, U?, D?..etc. Also, I am looking for refdes reuse setup. For example, I have deleted R5 and R7, how to I make the later added refdes does not use R5 and R7, but continue from the largest value. Or, vise versa. Any ideas?Your helps are much appreciated.
Just posted this elsewhere in the forum - use this to reset refdes (LOCATION)"Use Tools->Global Update->Global Property ChangeThs can be used to change property values across the design, sheet or module - you'll need to change LOCATION and $LOCATION, preserve the source property and reset the value to ?. Make sure that you take a backup - this will affect placement if a brd (PCB) exists."The refdes don't need to be reset to R?, C? - just a ? will do. The library definition for the parts (chips.prt file) will have a definition for the prefix (PHYS_DES_PREFIX), and this is used by the Packager (Export Physical) to assign the prefix.In the Advanced tab of the Packager, click on the Advanced button in the Package Option section, then click on the Layout tab, in here is a tick box for Reuse Refdes numbers - this controls whether the refdes is used again or the next number is used
Hi Andrew,Thank you for your quick reply. Please allow me to ask further, because I followed your description and ran into a couple problem.
"Use Tools->Global Update->Global Property Change Checked!Here is my selection:--------------------Name-----------Value-------------Change: LOCATION *(wildcard)To: LOCATION ?And selected for entire design on components, and save after change. Everything ran, and seems to work, I now see ? on the schematics everywhere. Now comes the quesiton. 1. When I tried to save the design, it returns error saying ' (placeholderprops) Place holder property needs value set.' for all the ?2. So, I turned off error checking and tried to export the design to regenerate the refdes, however, it returns error message say the following " Existing hard LOCATION property in drawing was left unchanged."Any more hints?Thanks for your help, Jason Huang
Hi JasonThere's 2 levels of property in DEHDL - soft and hard. Soft properties are typically system assigned (like by the packager when Export Physical is run), and these soft properties do not need to be set (can have a value of ?). Hard properties are set by the user and need to have a value (other than ?) otherwise an error is generated on Save in DEHDL.The LOCATION property is a hard property, the equivalent soft property is $LOCATION - so in the sch everything that has a LOCATION property needs to have a value set to save without an error.It sounds like your schematic used hard LOCATIONS - which leaves you with 2 options:-1. Manually set all the LOCATION properties2. Change the LOCATION property to $LOCATION (using Global Update)The second is the easiest - once this is done the sch should save and export physical OK (as long as there are no other errors), and the $LOCATION property will be populated by backannotation.CheersAndy
Hi Andy, Great!, I got it working and realize what Cadence reference where talking about regarding soft and hard properties. Now we have a bunch of happy engineers.: )Slancha! Jason Huang
CoolHave a look into the soft/hard properties - you can have a mixture of these, and potentially get a conflict between a hard and soft property. In this case the hard property is preserved and the soft property will be changed, so that no conflict occurs.In some cases you need to use soft properties, like replicated hierarchy (but not design reuse), so that the different occurences can be managed - use Tools->Occurence Edit Mode to see the "real" values in these situations