Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm trying to get both the associated hole tolerance from a padstack definition and the defined "DEFAULT INTERNAL" pad(s) using the Allegro SKILL api.
I am able to extract all other portions of the padstack definition except for these two pieces of information. I have tried iterating over the "pads" property of the padstack but the "DEFAULT INTERNAL" pads are mysteriously absent. Similarly, axlDBGetPad is not able to retrieve the pads (as far as I can tell). There are definitely default internal pads defined for the padstacks.
For the drill tolerance I can't seem to find anything about how to retrieve the tolerance values in the documentation. All other drill properties (drillOffset, drillDiameter, etc.) are associated with the padstack definition object and are perfectly readable, but the hole tolerance is mysteriously missing.
I've scoured the Allegro SKILL documentation but can't seem to find any information on these issues.
Any help or advice would be appreciated. Thank you.
I'm using Allegro 16.3
Unfortunately you will have to use an extract routine to get the tolerance values. Look for DRILL_HOLE_POSTOL and DRILL_HOLE_NEGTOL in ncdrill_view.txt. You mmight like to raise an enhancement request to get these added as attributes.
By loading a padstack you should be able to determine the default internal pad:
padstack = axlLoadPadstack(padName)
internalPad = car(setof(pad, padstack ->pads, pad ->type == "REGULAR" && car(parseString(pad ->layer, "/")) == "ETCH" && !member(cadr(parseString(pad ->layer, "/")), '("TOP", "BOTTOM"))))
In reply to eDave:
Thanks for your reply Dave.
Ah, I feared the drill tolerances might not be accessible as simple properties.
The method you outlined for the default internal pads does not seem to work in my case. Specifically, I'm attempting to read the default internal pads in the context of a package symbol loaded in the symbol editor. When accessing the padstack pads (padstack->pads) through the SKILL console it only retrieves pads for following layers:
In reply to stburton:
I feel your pain!
Again, I think you have to use extracta. Look for PAD_STACK_INNER_LAYER
Assuming you are using 16.5 although these might work in earlier releases...
- You can get the internal definition (DEFAULT INTERNAL) by doing using the 'internal symbol as the 2nd arg to GetPad
pad = axlDBGetPad(pin 'internal "REGULAR")
- For toleranace you need to access the padstack. For example if you have a pin dbid assigned to variable "pin". Then you would:
def = pin->definition ; get padstack
; tolerance is represented as a list of (+tol -tol) in design units (float)
printf("tol %L\n" def->holeTolerance)
In reply to fxffxf:
I'm on 16.3 but both methods you suggested seem to work in 16.3.
How did you know to use the 'internal symbol to retrieve the internal pads for axlDBGetPad? I couldn't seem to find it documented anywhere.
I don't know how I missed the "holeTolerance" property on the padstack definition, could have sworn it was missing the other day.
Thanks again to everyone who replied.
could be a couple of reasons:
- the functionality was added in a hotfix
- it was missed in the offical doc
Seeing that the 16.5 offical doc (cdnshelp) has it then it might have been added to 16.3 via a hotfix. The unoffical doc can sometimes have info not in the real doc. This is @ <cdsroot>/share/pcb/examples/skill/DOC/FUNCS
Being on UNIX, I find it is easier to use the unoffical doc since I can search by using 'grep'. The unoffical doc doesn't contain drawings but the axl Reference manual doesn't have many of them.