Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
If on the same net DRC, due to the stack via design. Alot of DRC will apply also.
Is there a way to identify this issue? Pls advice.
Wouldn't it be easyer to setup drc rules to accept stacked via 's ?
In reply to Romme:
My problem is how to detect 2 same via overlap each other but has slight different xy position at same layer?
These 2 vias have same net. So, if I on the same net drc, I will get alot of drcs.
In reply to Alice:
Here's some code for you to try:
defun( getDuplicateHoles (locs @key blindBuried, (tol axlMKSConvert(0.2 "mm"))) let((loc, dupes) while(locs loc = car(locs), locs = cdr(locs) if(blindBuried then when(setof(pt, locs, and(cadr(pt) == cadr(loc), samePoint(car(pt), car(loc), tol))) dupes = cons(loc, dupes) ) else when(setof(pt, locs, samePoint(pt, loc, tol)), dupes = cons(loc, dupes)) ) ) dupes))
defun( same (x1, x2 @optional tolp, tolm) unless(tolp, tolp = expt(10, -2 - cadr(axlDBGetDesignUnits()))) cond( (!x1 && !x2, t); Both are nil (!x1 || !x2, nil) ; One, and only one, is nil (!tolm && abs(x1 - x2) > tolp, nil) (tolm && x1 - x2 > tolp, nil) (tolm && x2 - x1 > tolm, nil) (t, t) ))
defun( samePoint (pt1, pt2, @optional tolp, tolm) unless(tolp, tolp = expt(10, -2 - cadr(axlDBGetDesignUnits()))) and(same(car(pt1), car(pt2), tolp, tolm), same(cadr(pt1), cadr(pt2), tolp, tolm)))
In reply to eDave:
This is exactly the type of issue that I am trying to address - duplicate drills with the exact same xy and touching drills and then create a report file for them. Fab shops desire the report file so they can modify the NC drill file so not to make double or more hits on a single hole. Is it possible for you to expand on your code slightly to create a simple report file? The duplicate drills are also counted in the drill legend, but that is another issue.
In reply to Marathon:
defun( getDuplicateHoles (objs @key (tol axlMKSConvert(0.2 "mm"))) let((obj, loc, closeObjs, dupes, p) while(objs obj = car(objs), objs = cdr(objs), loc = obj ->xy closeObjs = setof(o, objs, and((car(o ->startEnd) == car(obj ->startEnd) || cadr(o ->startEnd) == cadr(obj ->startEnd)), samePoint(o ->xy, loc))) when(closeObjs dupes = cons(sprintf(nil, "%s at %L clashes with %s at %L", axlPPrint(obj ->objType), obj ->xy, buildString(unique(closeObjs ~>objType), ", "), closeObjs ~>xy), dupes) ) ) if(dupes then p = axlDMOpenFile("MISC", "duplicateHoles.txt", "w") fprintf(p, "Duplicate holes:\n\n") foreach(dupe, dupes, fprintf(p, "%s.\n", dupe)) axlDMClose(p) axlUIViewFileCreate("duplicateHoles.txt", "Duplicate holes", nil) else println("No duplicates found.") ) dupes))
defun( getDuplicateHoles (@optional netName) let((oldSetData, holeObjects) oldSetData = list(axlGetSelSet(), axlGetFindFilter(nil), axlGetFindFilter(t)) axlClearSelSet() axlSetFindFilter(?enabled '("noall", "pins", "vias", "invisible"), ?onButtons '("noall", "pins", "vias")) axlAddSelectAll() holeObjects = setof(obj, axlGetSelSet(), obj ->isThrough) when(netName, holeObjects = setof(obj, holeObjects, obj ->net ->name == upperCase(netName))) axlSetFindFilter(?enabled cons("noall", cadr(oldSetData)) ?onButtons cons("noall", caddr(oldSetData))) axlSingleSelectObject(car(oldSetData)) getDuplicateObjects(holeObjects)))
defun( getDuplicateObjects (objs @key (tol axlMKSConvert(0.2 "mm"))) let((obj, loc, closeObjs, dupes, p) while(objs obj = car(objs), objs = cdr(objs), loc = obj ->xy closeObjs = setof(o, objs, and((car(o ->startEnd) == car(obj ->startEnd) || cadr(o ->startEnd) == cadr(obj ->startEnd)), samePoint(o ->xy, loc))) when(closeObjs dupes = cons(sprintf(nil, "%s at %L clashes with %s at %L", axlPPrint(obj ->objType), obj ->xy, buildString(unique(closeObjs ~>objType), ", "), closeObjs ~>xy), dupes) ) ) if(dupes then p = axlDMOpenFile("MISC", "duplicateHoles.txt", "w") fprintf(p, "Duplicate holes:\n\n") foreach(dupe, dupes, fprintf(p, "%s.\n", dupe)) axlDMClose(p) axlUIViewFileCreate("duplicateHoles.txt", "Duplicate holes", nil) else println("No duplicates found.") ) dupes))
Someone owes me a beer!
Thanks Dave! I will ship you a case. Name your brand :)
I will look closer as to why the report only finds pins that have the exact same xy and not ones that are slightly overlapped. Vias are also not found, but it is a tremendous start!
Free stuff always has bugs;)
I'd forgotten the tolerance. Here's the corrected function:
Incredible program Dave. I have found it useful already.
Our boards have alot of Ground stitching which could result in duplicates if you are not paying attention.
In reply to Geoff:
Thanks for this and other feedback.
I'll put it together into a small Skill utility with a form - and a few other enhancements - and publish next week.
As promised, attached is the utility. Thanks to those who provided input and feedback - especially Marathon.
As always, feedback is welcome.
Ok, (my last post got lost)
; Installation instructions:;; Install findDoubleHitHoles_public.il into your skill folder.; Add load("findDoubleHitHoles_public.il") to the allegro.ilinit file in your pcbenv folder.;; Running within Allegro:; Type "find double hits" (without the speech marks) in the command window.