Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
From my previous post I've found out how to color pads and vias of the certain spacing class that I'm looking for. As the title states, now I'm trying to extract and print information from those nets to a report. Basically I want to parse through all of the nets and filter out/select all of the pads/pins with that spacing class property which I do by using this code:
;Select all nets/pins
axlSetFindFilter( ?enabled (list "noall" "pins" "invisible") ?onButtons (list "pins"))
pins = axlGetSelSet()
csetNets1 = axlSelectByProperty("net", "SPACING_CONSTRAINT_SET", "TYPE1")
;;Extract which nets have the spacing class property "TYPE1"
cset1_pins = setof(pin, pins, member(pin ->net, csetNets1))
From there I want to take csetx_pins and print them out to a report.. I want the report to look like this:
CurrentTime : Mar 25 09:31:46 2013
Pin name x coord y coord Mirrored? Rotation SPAC_CLASS PAD_NAME Net_name
Q7.2 58.5 23.0 NO 270 degrees TYPE1 SR061X046 CONT_+3.3V
C1807.2 26.0 23.0 NO 270 degrees TYPE1 SR110X100 CONT+5V
Q2.1 42.0 23.0 NO 270 degrees TYPE2 SO220X064 GND
Q3.2 58.5 23.0 YES 270 degrees TYPE1 SR061X046 CoNT_+3.3V
C17.2 26.0 23.0 YES 270 degrees TYPE2 SR110X100 CONT+5V
Q9.1 42.0 23.0 YES 270 degrees TYPE3 SO220X064 GND
Here's what I have so far:
cl_file = outfile("net_list.rpt" "w")
; ------ Print Header
; ------ Print CurrentTime
fprintf(cl_file "CurrentTime : %s \n" getCurrentTime())
; ------ Print column headers
fprintf(cl_file "Pin name \t x-coord \t y coord \t Mirrored? \t Rotation \t Spacing class \t Pad type \t Net name\n")
fprintf(cl_file "%s \t\t %L\t\t %s\t\t %4.0f degrees \n" ref_des xy_loc mirrorstatus rotationstatus)
You would need to do more work get to the spacing cset is assigned using groups (netclass, bus, diffpair, etc.) For example, you place the nets into NetClass' and then assign the spacing cset at the net class level. You can use
after step 2 and then get the SPACING_CONSTRAINT_SET off of the netclass