Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm trying to write a code to check fillet , but I don't know how to know if a shape is "fillet shape". My version is 16.3( in this, when i show element fillet shape => "Shape is fillet"). Pls help me ?
If you have the dbid of a shape then
shape->fillet == t
if the shape is a fillet shape
In reply to fxffxf:
Thank for your advice ! That is what I need.
One more question that is How to know a fillet shape is belong to which cline? When I show element a fillet shape, i found that It's only connect to a via or a pin. Can you help me do that.
In reply to luanvn81:
You can explore the axlDBGetConnect function by passing the dbid for shape as input and getting the parent Net or Cline etc
In reply to Pawandeep:
Hi Pawandeep !
I have tested follow your advice, by passing the shape's dbid to get parent of Cline, It got all clines of the shape's net . So I don't know which cline belongs to processing shape. Another suggestion ?
What is your purpose?
I want to
check fillet at pins and vias with the condition is: if one Cline connect to
pin(or via) which clinewidth >0.3mm
then skipping. It's only check clines that clinewidth <= 0.3mm.
In this case it will be easier to use function axlFillet for adding fillets.
You can pass the cline/net dbid which have width lesser than your target.