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Hello, LEC between RTL and gate level after gated clock insertion reports all the gated clock latches as "Unreachable". Is there some constrain or command in LEC which should be implemented to resolve this issue?
Thank you very much!
This is expected behaviour. During modeling Conformal takes the latch circuit and changes it back to a mux so equivalence checking can be run. Please see Solution 11195852 for more details.
In reply to croy:
Thank you very much!
you can use the flatten model with the option -gated_clock
Set Flatten Model -Gated_Clock
In reply to AMit Raj:
set flatten model -gated_clock will apply on the golden code or revised code?
set flatten model -seq_constant will be applied on the golden code or revised code?
In reply to piyushoct:
The options will be applied to both (so there is no -golden or -revised option but there is for remodel). I'm pretty sure those options will be applied in a matching manner. So it will apply to one side if it exists in the other. But won't if it doesn't match.
In reply to tstark: