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Hi,I'm tyring to validate whether the CTS step has considered the macromodel definitions I defined in the clock spec file for the blocks during my CTS at the Top Level i.e. Full Chip Level.I have the following macro model defined on a particular block. block_abc is the module/cell name of the block and clk is the pin on which I defined the macromodel.#MacroModel pin <pin> <maxRiseDelay> <minRiseDelay> <maxFallDelay> <minFallDelay> <inputCap>MacroModel port block_abc/clk 453.3ps 285.1ps 478.8ps 307.6ps 0fF hold_func level 15 8MacroModel port block_abc/clk 981.5ps 776.1ps 1052ps 766.1ps 0fF setup_func level 15 8In the clock.report which the encounter dumps after the CTS step, I see the following behavior:Min trig. edge delay at sink(R): block_abc_inst/clk 4750.4(ps) *Mmodel*However, when I try to get the latencies for all the block clock pins at the Top Level, the block_abc_inst/clk has the following latency.report_clock_timing -to block_abc_inst/clk -type latency ---Latency--- Source Network Total Clock Pin--------------------------------------------------------------------------- 0.000 3.166 3.166 f block_abc_inst/clk
So, I'm just wondering whether the tool is including the macromodel defn (i.e. the delay associated) when i execute the above command?
The main reason for the question arised due to the fact that I'm seeing approximately the same latency at the clock pins for all the blocks in the Top Level, inspite of these blocks having different delay values in their respective macromodel definitions. All these blocks are driven by the same clock.
In reply to Vishnu Chada:
Thanks for the info. I tried doing what you've said i.e. executed the "cleanupSpecifyClockTree" command.
Following the cleanup of clock spec, I reported the latency to the same block clock pin and I see the same latency number.
I also did a report timing to the same block clock pin. I see the same latency number. So, it probably looks like the tool is not accounting for the macromodel definitions while building the clock tree to the block clock pins. Also, as I mentioned earlier, all the blocks are having the same latency values inspite of them having different macro model delay values.
This is something very important from a Top Level CTS perspective.
Any further suggestions please?
In reply to gsc104:
Where are you specifying the macromodels when you run CTS? If the macromodel is used correctly, then you should be able to look in the clock.report file that CTS generates and look at the insertion delay to the macro in question. Let's say you have a clk with an insertion delay of around 2 ns, and a macromodel for a macro that has a delay of 1ns. In the clock.report file, if you look at just any flop on the clk tree, you should see a delay of around 2ns, but if you look at the delay for the macro, it should be around 1ns (1ns delay + 1 ns macromodel delay = 2ns total). Do you see something like this?
Typically, we have the macromodel lines at the top of the .ctstch file. Is that where you are specifying them?