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We are performing postlayout simulation for a digital design which adopts TSMC 65nm standard cell library. During SDF back annotation by Verilog-XL 8.2, there are many SDFA errors, "Failed to find SETUP timingcheck" and "Failed to find HOLD timingcheck". But the simulation is still passed. Is it caused by mismatch Verilog model of the standard cells? or by improper EDA tools? Is it important?
It sounds like the timing checks in your verilog model do not match those in your .lib files. The SDF is generated based on the timing in the .lib file. During back-annotation, it tries to match the SDF timing to a timingcheck in the verilog model. What appears to be happening above is that during back-annotation, it can't find the setup and hold timing checks in your verilog model.
If this is what's happening, it is important, because even though the simulation is passing, it may be passing without performing setup and hold timing checks.
Check in you ncelab/irun log file for:
Annotating SDF timing data: Compiled SDF file: Your_Design.sdf.X Log file: logs/design.log Backannotation scope: tb.dut Configuration file: MTM control: MINIMUM Scale factors: 1:1:1 Scale type: Annotation completed with 0 Errors and 16 Warnings
Do you have any Errors ?
In reply to Scrivner:
I would like to know if the SDF is generated based on the timing in the .lib file, why is it not able to find the setup and hold timing checks in the verilog model which is in general generated by synthesizer or modified by router according to the same .lib file?
In reply to timchung:
The verilog models are not generated by synthesis or modified by the router. I think you might be referring to instantiations of gates in a netlist (which are synthesized and affected by the router).
The verilog models I was referring to are the verilog library of the standard cells. These define the funtions and behaviors of the gates instantiated in the netlist. They are used by ncverilog to simulate the instances in the netlist.
What you need to do is look at the timingcheck section for a flop in the SDF file and compare it to the timingcheck section in the verilog model of the same cell. For each timing check in the SDF, there should be a matching timing check in the verilog model. This matching timing check in the verilog model is what the SDF back-annotates to. When there is a timing check in the SDF that does not have a matching timing check in the verilog model, there is nothing for that SDF timing check to back-annotate to. That is when you get an error or warning like the ones you are seeing.
I have a situation similar to that of this thread. Some of our cells have sdf annotations unspecified in the verilog (giving a elaboration warning), but I also have missing sdf annotations requested in the verilog (thus leaving the default check values of 1 ns). I looked a bit but I'm still stuck.
Basically, if I use my hdl compiler to generate a sdf without RC, I get everything I need, and the elaborator does not complain. In this sdf, I have 3 setup checks, 3 hold checks and 3 width checks.
When I use encounter, I get 3 width checks, 2 setuphold checks and 1 recrem check. From the pin names of the recrem I'm pretty sure this sdf annotation replaced the missing setup/hold pair that I'm looking for. I tried telling encounter to use version 2.1 sdf with the -remashold switch, and got one more hold, related to a recovery (which is of course not in the verilog specify block).
Any ideas on which end to work? Add/modify the specify fields in the verilog, or work out how to write out the necessary fields in the sdf? I'd like to give more details, but I'm not sure what could be useful at this point.