Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I have to setup a chip with 5 completely separated cores. Each core has its own vcc_core/io and vdd_core/io ind i/o pins.
But the actual voltage of all cores is 1.8V. For testing only one core should be active at a time.
Can I do this just with connectGlobalNet or is this more like a multi supply voltage flow with a single volate?
If there is some documentation about this topic, please give me a hint. The UserGuide didn't cover this topic.
It almost sounds like you can just use globalNetConnect, but when you say that only one core should be active at a time, that implies domains controlled by power-switch cells, which is more complicated. There is a Low Power Design chapter in the EDI user guide, have you reviewed that? If you need further info, search for Low Power on support.cadence.com. There will be some other documentation there.
In reply to Kari:
Hi Kari, thanks for the reply
To make it clearer: We are only powering one core via external vcc at a time. There is no need for power switches. The used lib even does not have and power awareness. My problem in the moment is, that the power supply lines of the standard cell rows are always connected to the last used vcc_core$.
what I have is one toplevel module which instanciates the 5 cores. than i create a fence for each core, create the powerrings around the fence and connect the pin vdd_core (only under module core1) to global net vdd_core1. the same for cores 2 to 5.
how can i restrict sroute to only route the standard cell vdd lanes inside the area of the module fences? outside the fences there will be no logic at all, only wires.
In reply to schnufff:
Ok, this should be pretty easy then. You might want to look at globalNetConnect -module to assign the different sources to the different core hierarchies.
For sroute, try putting placement blockages between the core fences. That should stop the followpin generation from happening between fences. If I've misunderstood, please post a picture - I'm sure we can get the tools to do what you want here.
sorry for the late reply. I was busy with paperwork. I managed to connect the global nets correctly and also constrainted the follow pins as you suggested. Now the next problem: When I add TieHiLow cells or do CTS, how can I control to which vcc_core_x (x in 1 to 5) the by Encounter added cells will be connected.
All cores are surrounded by a placement blockage as you suggested. All buffer/inverters added by CTS and the TieHighLow cells should be placed inside the corresponing fence andconnect the the vdd,vcc already routed there.
Thanks in advance