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Hello, I'm a graduate student at the EE faculty, Technion, Israel. I'm currently working on a thesis on static power analysis of circuit level. For that purpose, I first review existing power analyzing tools. It will be very helpful if you could answer me the following short questions, or point me to where I can find this information. If you wish, I'll be happy to send you the complete review of existing tools one I finish it. My questions are: 1. Does your tool run on circuit level or on RTL? I'm interested in circuit level power analyzers. 2. Is you tool static or dynamic? i.e. does it actually simulate the circuit using circuit simulator, or just model the behavior (or both - for instance dynamically simulates leakage and statically models switching power) 3. Is there a separate report for each power component (CV^2, rush through, leakage, glitch, overshoot power etc.)? 4. Does your tool handle only cell based design (that require pre-characterized cells) or transistor-based design as well? 5. If possible - how do you model the different power components (how do you calculate the capacitance for the CV^2 model, the leakage, the rush through etc.) in non-cell based design 6. Does your tool contain power optimizer? 7. Do you report the max/min leakage? 8. Any additional feature that distinguish your tools from others? 9. Are there any published papers describing the architecture of your tool? You help is very much appreciated. Thank You, Yoni Aizik.
hi friend According to my view CDN wont have any circuit level power analysis tools and circuit level power optimazation done one any synthesis tool. tools like RTL compiler calculate power according to internal power(gate dynamic power) + net power+ leakage power of every indivitual gates. According it makes a database and calculate the total power of the domain/module/chip. My advice for u try to see any Transistor Level Power Analysis Tools whether it can do all dynamic power calculation ? this is way understand ur problem and answer it. reply ur comments thanks