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I am working on implementing a block using FE. Usually, after I finally achieve timing-closure, I will dump/save verilog netlist and verilog-In the netlist into Cadence dfII to create new schematic for the block, which will reflect the netlist changes from IPO/CTS. However, at this time, front-end team has a customized top level schematic: lower level symbols are located in proper places; all the wire connections are hand-drawn and clearly labeled... They love it so much and don't like to lose it. So, they asked me whether or not it is possible to tell FE only put changes to lower level modules duing CTS/IPO and keep top level untouch even during IPO/CTS, then, we only need to verilog-in the lower level module into dfII and top level schematic that they love will survive.
Any body has tried the similar or have a good idea to achieve this?
I don't know of an easy way to make this happen. You could write a script to identify the top-level nets in the design and "dont_touch" them- the downside to this would be that the portion of the top-level nets in the design would also be dont_touched which would limit optimization more than you'd like perhaps. Another approach would be to the partition the design and only optimize the design within each of the partitioned blocks which would have the effect you're seeking I believe.
In reply to Robert Dwyer:
Thank you very much for your advice. Since there are so many sub-modules in this block, partitioning the block may be too much for me to do although it may be a very good idea in other situations. I will try the "dont_touch" on the top-level nets and see how far I can go.