Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
My job involves taking a routed design and changing some of the cells and routing them to the cells that already exist.
I looked at some ways, and the most obvious way is to manually "Add Wire" option in Encounter. Is there any way to tell the routing tool built in (like sroute) to route the cell for me? For example, I would like to route (or connect) a cell MY_CELL1/PortA (where PortA is the port of this cell) to MY_CELL2/PortB.
Can I use sroute? If yes, then, can someone please throw a hint as to how?
Any other method? I am sure that some method should exist, which should avoid manual "Add Wire" method.
Would appreciate any help!
Incremental capabilities aside for a moment, which automatic routing function you should use in general depends on the nature of the signals being routed. NanoRoute (ie, "globalDetailRoute") is typically used for routing signal and clock nets. "sroute" is typically used for routing power/ground connections so it doesn't seem well-suited to your purpose (I'm inferring this from the PortA/PortB names you mentioned rather than VDD/VSS).
Automatic routers in the tool rely on logical connections being in place which instruct the router as to which connections should be made. For signal nets, these connections are determined from the input Verilog netlist primarily, which can be altered in-session with ECO commands like "addInst", "addNet", and "attachTerm". You could verify these connections by clicking the terminals and querying their net and flight lines.
Once these connections are logically in place, you can proceed with incrementally routing them with "globalDetailRoute". It would probably be good to "setNanoRouteMode -routeWithEco true" to inform the tool that routing is present and the tool should incrementally refine the routing.
Hope this helps,Bob
In reply to Robert Dwyer:
Thanks for your advise. After tinkering around a bit, I was able to run ECO process. It was a tad tricky, since I was using an older verion of Encounter, which did not have "ecoDesign"