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I'm using SOCE for P&R and I keep getting this spacing error with the pad fillers:
Pin of Cell IN0_5 & Blockage of Cell pfill_W_44
I cannot seem to resolve it. What could be the problem?
In reply to vishnu:
Thanks for responding!
Attached are some of the pics detailing the errors.
There are 2 main DRCs, one between the fillers etc. and the other is the special route to the power I/O pads.
In reply to Mooty:
The first picture looks like nanoRoute is trying to route some nets that are really connected by abutment of the IO cells. You should place a -skip_routing attribute on these nets:
setAttribute -net net1 -skip_routing true
The second picture looks like a violation between the route to the IO pin and the blockages around the IO pin. These may or may not be real violations - you'll have to run your signoff DRC to be sure.
I'm not sure about the other two.
In reply to Kari:
Thanks a lot for your help.
The first case, however, is actually the connection between the power pads and the power ring. This connection is necessary right?
I have another problem now.
Apparently, there are some DRCs between the power stripe and the cells beside it. The error seems related to the clock as all of the errors have the clock present.
For the first issue, if you mean that the IO ring is connected by abutment but you are seeing violations, it could be blockages causing verify geometry to think there is an error where there really isn't. You can try turning on/off some of the ver geom settings and see if you get different results. The real test is signoff DRC. Does it show any problems in your IO ring?
For the second issue, it's hard to tell from this picture (not everything is turned on), but it looks like you have a wide metal (the power) too close to regular routing. Maybe your clock routes are double-width? I'm not sure. Turn on signal routing and see if you can tell what the error marker is flagging. The text description should also shed some light.
with regards to the second issue,
The error message is of this form:
SPACING: Regular Via of Net Final/CLK__L7_N231 & Special Wire of Net vdd! ( M2 )Bounds : ( 2746.350, 711.800 ) ( 2747.100, 712.600 )Actual: 0.75 Min: 0.8
I still can't figure out how to solve this problem. Is this a placement problem?
You have a spacing violation between the m2 in the via on the C pin and the m2 bus on the left. (I think your nets are not displayed because you are in floorplan view instead of physical view.) Once you get the nets displayed, the error should be clear.