Typically, separate preCTS and postCTS files are used to adjust the values associated with "set_clock_uncertainty" and sometimes the set_min/max_delay values to account for propagated clocks.
However, in your case (thanks for the attachment, it is very helpful) it appears that the postCTS SDC contains the following types of additions:
Hope this helps,Bob
In reply to Robert Dwyer:
In reply to tsahi:
The first 2 items are minor (or perhaps meaningless depending on the caveats I mentioned in italics above). The 3rd item (set_clock_latency) is actually quite important and if not included it would invalidate your IO timing.
I just wanted to mention that the set_propagated_clock statements can also be important if you're not using Restore Design to bring your data up in Encounter. Most of the time, we read in verilog, def, and SDC (Import Design, defin, loadTimingCon) and if it's a postCTS design, we need to have the set_propagated_clock lines in the SDC file. So we always have a postCTS SDC file, even if that's the only difference. (We call the preCTS file design.ideal.sdc and the postCTS file design.prop.sdc.)